ST SPC560P34 - Table 308. PDEDR Field Descriptions; Figure 299. Power-Down Exit Delay Register (PDEDR); Delay Registers

RM0046 Analog-to-Digital Converter (ADC)
Doc ID 16912 Rev 5 601/936
23.4.8 Delay registers
Power-Down Exit Delay Register (PDEDR)
23.4.9 Data registers
Introduction
ADC conversion results are stored in data registers. There is one register per channel.
Channel Data Registers (CDR[0..15])
CDR[0..15] = precision channels
Each data register also gives information regarding the corresponding result as described
below.
Figure 299. Power-Down Exit Delay Register (PDEDR)
Address: Base + 0x00C8 Access: User read/write
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000
PDED
W
Reset0000000000000000
Table 308. PDEDR field descriptions
Field Description
PDED
Delay between the power-down bit reset and the start of conversion. The delay is to allow time for the
ADC power supply to settle before commencing conversions.
The power down delay is calculated as: PDED x 1/frequency of ADC clock.