RM0046 Introduction
Doc ID 16912 Rev 5 55/936
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels.
The eDMA module provides the following features:
● 16 channels support independent 8-, 16- or 32-bit single value or block transfers
● Supports variable-sized queues and circular queues
● Source and destination address registers are independently configured to either post-
increment or to remain constant
● Each transfer is initiated by a peripheral, CPU, or eDMA channel request
● Each eDMA channel can optionally send an interrupt request to the CPU on completion
of a single value or block transfer
● DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer
and CTU
● Programmable DMA channel multiplexer allows assignment of any DMA source to any
available DMA channel with as many as 30 request sources
● eDMA abort operation through software
1.6.4 Flash memory
The SPC560P40/34 provides 320 KB of programmable, non-volatile, flash memory. The
non-volatile memory (NVM) can be used for instruction and/or data storage. The flash
memory module is interfaced to the system bus by a dedicated flash memory controller. It
supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to
flash memory. The module contains four 128-bit wide prefetch buffers. Prefetch buffer hits
allow no-wait responses. Normal flash memory array accesses are registered and are
forwarded to the system bus on the following cycle, incurring two wait-states.
The flash memory module provides the following features:
● As much as 320 KB flash memory
– 6 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 128 KB) code flash memory
– 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash memory
– Full Read-While-Write (RWW) capability between code flash memory and data
flash memory
● Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch
buffers can be configured to prefetch code or data or both)
● Typical flash memory access time: no wait-state for buffer hits, 2 wait-states for page
buffer miss at 64 MHz
● Hardware managed flash memory writes handled by 32-bit RISC Krypton engine
● Hardware and software configurable read and write access protections on a per-master
basis
● Configurable access timing allowing use in a wide range of system frequencies
● Multiple-mapping support and mapping-based block access timing (up to 31 additional
cycles) allowing use for emulation of other memory types
● Software programmable block program/erase restriction control
● Erase of selected block(s)
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