ST SPC560P34 User Manual

Enhanced Direct Memory Access (eDMA) RM0046
384/936 Doc ID 16912 Rev 5
18.4.2 Debug mode
If enabled by EDMA_CR[EDBG] and the CPU enters debug mode, the eDMA does not grant
a service request when the debug input signal is asserted. If the signal asserts during a data
block transfer as described by a minor loop in the current active channel’s TCD, the eDMA
continues the operation until the minor loop completes.
18.5 Memory map and register definition
18.5.1 Memory map
The eDMA programming model is partitioned into two regions:
Region 1 defines control registers; Region 2 defines the local transfer control for the
descriptor memory.
Table 175 is a 32-bit view of the eDMA memory map.
Table 175. eDMA memory map
Offset from
EDMA_BASE
(0xFFF4_4000)
Register Location
0x0000 EDMA_CR—Control Register on page 18-386
0x0004 EDMA_ESR—eDMA Error Status Register on page 18-386
0x0008 Reserved
0x000C EDMA_ERQL—eDMA Enable Request Register on page 18-389
0x0010 Reserved
0x0014
EDMA_EEIRL—eDMA Enable Error Interrupt
Register
on page 18-390
0x0018
EDMA_SERQR—eDMA Set Enable Request
Register
on page 18-391
0x0019
EDMA_CERQR—eDMA Clear Enable Request
Register
on page 18-392
0x001A
EDMA_SEEI—eDMA Set Enable Error Interrupt
Register
on page 18-392
0x001B
EDMA_CEEI—eDMA Clear Enable Error Interrupt
Register
on page 18-393
0x001C
EDMA_CIRQR—eDMA Clear Interrupt Request
Register
on page 18-393
0x001D EDMA_CER—eDMA Clear Error Register on page 18-394
0x001E EDMA_SSBR—eDMA Set START Bit Register on page 18-395
0x001F
EDMA_CDSBR—eDMA Clear DONE Status
Register
on page 18-395
0x0020 Reserved
0x0024 EDMA_IRQRL—eDMA Interrupt Request Register on page 18-396

ST SPC560P34 Specifications

General

Brand	ST
Model	SPC560P34
Category	Microcontrollers
Language	English