ST SPC560P34 - Figure 411. DMA Request 0 Select Register (DREQ0); Figure 412. DMA Request 1 Select Register (DREQ1); Table 383. ENBL Field Descriptions

RM0046 eTimer
Doc ID 16912 Rev 5 727/936
DMA Request Select registers (DREQ0, DREQ1)
Table 383. ENBL field descriptions
Field Description
ENBL
Timer Channel Enable
These bits enable the prescaler (if it is being used) and counter in each channel. Multiple ENBL
bits can be set at the same time to synchronize the start of separate channels. If an ENBL bit is
set, then the corresponding channel will start counting as soon as the CNTMODE field has a value
other than 000. When an ENBL bit is clear, the corresponding channel maintains its current value.
0 Timer channel is disabled.
1 Timer channel is enabled. (default)
Figure 411. DMA Request 0 Select register (DREQ0)
Address: Base + 0x0110 Access: User read/write
0123456789101112131415
R00000000 000
DREQ0[4:0]
W
Reset0000000000000000
Figure 412. DMA Request 1 Select register (DREQ1)
Address: Base + 0x0112 Access: User read/write
0123456789101112131415
R00000000 000
DREQ1[4:0]
W
Reset0000000000000000