ST SPC560P34 - Table 181. EDMA_CERQR Field Descriptions; Figure 182. Edma Clear Enable Request Register (EDMA_CERQR); Figure 183. Edma Set Enable Error Interrupt Register (EDMA_SEEIR)

Enhanced Direct Memory Access (eDMA) RM0046
392/936 Doc ID 16912 Rev 5
eDMA Clear Enable Request Register (EDMA_CERQR)
The EDMA_CERQR provides a simple memory-mapped mechanism to clear a given bit in
the EDMA_ERQRL to disable the DMA request for a given channel. The data value on a
register write causes the corresponding bit in the EDMA_ERQRL to be cleared. Setting bit 1
(CERQn) provides a global clear function, forcing the entire contents of the EDMA_ERQRL
to be zeroed, disabling all DMA request inputs. Reads of this register return all zeroes.
eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
The EDMA_SEEIR provides a simple memory-mapped mechanism to set a given bit in the
EDMA_EEIRL to enable the error interrupt for a given channel. The data value on a register
write causes the corresponding bit in the EDMA_EEIRL to be set. Setting bit 1 (SEEIn)
provides a global set function, forcing the entire contents of EDMA_EEIRL to be asserted.
Reads of this register return all zeroes.
Figure 182. eDMA Clear Enable Request Register (EDMA_CERQR)
Address: Base + 0x0019 Access: User write-only
01234567
R00000000
W
CERQ[0:6]
Reset00000000
Table 181. EDMA_CERQR field descriptions
Field Description
0 Reserved.
1–7
CERQ[0:6]
Clear enable request.
0–15 Clear corresponding bit in EDMA_ERQRL
16–63Reserved
64–127Clear all bits in EDMA_ERQRL
Bit 2 (CERQ1) is not used.
Figure 183. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
Address: Base + 0x001A Access: User write-only
01234567
R00000000
W
SEEI[0:6]
Reset00000000