ST SPC560P34 - Table 461. DBCR2 Bit Definitions; Figure 509. DBCR2 Register

RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 875/936
Debug Control Register 2 (DBCR2)
Debug Control Register 2 is used to configure Data Address Compare and Data Value
Compare operation. The DBCR2 register is shown in Figure 509..
Table 461 provides bit definitions for Debug Control Register 2.
Figure 509. DBCR2 Register
SPR - 310
0123456789101112131415
R
DAC1US DAC1ER DAC2US DAC2ER DAC12M
DAC1LNK DAC2LNK
DVC1M DVC2M
W
Reset
(1)
0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000
DVC1BE
0000
DVC2BE
W
Reset0000000000000000
1. Reset by processor reset p_reset_b if DBCR0
EDM
=0, as well as unconditionally by m_por. If DBCR0
EDM
=1, DBERC0
masks off hardware-owned resources from reset by p_reset_b and only software-owned resources indicated by DBERC0
will be reset by p_reset_b.
Table 461. DBCR2 Bit Definitions
Bit(s) Name Description
0:1 DAC1US
Data Address Compare 1 User/Supervisor Mode
00 – DAC1 debug events not affected by MSR
PR
01 – Reserved
10 – DAC1 debug events can only occur if MSR
PR
=0 (Supervisor mode)
11 – DAC1 debug events can only occur if MSR
PR
=1. (User mode)
2:3 DAC1ER
Data Address Compare 1 Effective/Real Mode
00 – DAC1 debug events are based on effective address
01 – Unimplemented in e200z0h (Book E real address compare), no match can occur
10 – DAC1 debug events are based on effective address and can only occur if MSR
DS
=0
11 – DAC1 debug events are based on effective address and can only occur if MSR
DS
=1
4:5 DAC2US
Data Address Compare 2 User/Supervisor Mode.
00 – DAC2 debug events not affected by MSR
PR
01 – Reserved
10 – DAC2 debug events can only occur if MSR
PR
=0 (Supervisor mode)
11 – DAC2 debug events can only occur if MSR
PR
=1. (User mode)
6:7 DAC2ER
Data Address Compare 2 Effective/Real Mode
00 – DAC2 debug events are based on effective address
01 – Unimplemented in e200z0h (Book E real address compare), no match can occur
10 – DAC2 debug events are based on effective address and can only occur if MSR
DS
=0
11 – DAC2 debug events are based on effective address and can only occur if MSR
DS
=1