ST SPC560P34 - Table 459. DBCR0 Bit Definitions; Figure 507. DBCR0 Register

Nexus Development Interface (NDI) RM0046
870/936 Doc ID 16912 Rev 5
.
Table 459 provides bit definitions for Debug Control Register 0.
Figure 507. DBCR0 Register
SPR - 308;
0123456789101112131415
R
EDM
IDM
RST
ICMP
BRT
IRPT
TRAP
IAC1 IAC2 IAC3 IAC4
DAC1 DAC2
W
Reset
(1)
0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RET
0000
DEVT1 DEVT2
00
CIRPT
CRET
00000
W
Reset0000000000000000
1. DBCR0
EDM
is affected by j_trst_b or m_por assertion, and remains reset while in the Test_Logic_Reset state, but is not
affected by p_reset_b. All other bits are reset by processor reset p_reset_b if DBCR0
EDM
=0, as well as unconditionally by
m_por. If DBCR0
EDM
=1, DBERC0 masks off hardware-owned resources (other than RST) from reset by p_reset_b, and
only software-owned resources indicated by DBERC0 and the DBCR0
RST
field will be reset by p_reset_b. The DBCR0
RST
field will always be reset by p_reset_b regardless of the value of DBCR0
EDM
.
Table 459. DBCR0 Bit Definitions
Bit(s) Name Description
0EDM
External Debug Mode. This bit is read-only by software.
0 – External debug mode disabled. Internal debug events not mapped into external debug
events.
1 – External debug mode enabled. Hardware-owned events will not cause the CPU to vector to
interrupt code. Software is not permitted to write to debug registers {DBCRx, DBSR, DBCNT,
IAC1–4, DAC1–2} unless permitted by settings in DBERC0.
When external debug mode is enabled, hardware-owned resources in debug registers are not
affected by processor reset p_reset_b. This allows the debugger to set up hardware debug
events which remain active across a processor reset.
Programming Notes:
It is recommended that debug status bits in the Debug Status Register be cleared before
disabling external debug mode to avoid any internal imprecise debug interrupts.
Software may use this bit to determine if external debug has control over the debug registers.
The hardware debugger must set the EDM bit to ‘1’ before other bits in this register (and other
debug registers) may be altered. On the initial setting of this bit to ‘1’, all other bits are
unchanged. This bit is only writable through the OnCE port.
1IDM
Internal Debug Mode
0 – Debug exceptions are disabled. Debug events do not affect DBSR unless EDM is set.
1 – Debug exceptions are enabled. Enabled debug events will update the DBSR. If MSR
DE
=1,
the occurrence of a debug event, or the recording of an earlier debug event in the Debug Status
Register when MSR
DE
was cleared, will cause a Debug interrupt.