ST SPC560P34 - Table 47. Peripheral Status Registers 0; Figure 59. Peripheral Status Register 2 (ME_PS2); Table 47. Peripheral Status Registers 0...4 (ME_PS0...4) Field Descriptions

RM0046 Mode Entry Module (MC_ME)
Doc ID 16912 Rev 5 165/936
This register provides the status of the peripherals. Please refer to Ta b l e 47 for details.
Peripheral Status Register 2 (ME_PS2)
This register provides the status of the peripherals. Please refer to Ta b l e 47 for details.
Figure 59. Peripheral Status Register 2 (ME_PS2)
Address 0xC3FD_C068 Access: User read, Supervisor read, Test read
0123456789101112131415
R0 0 0
S_PIT
000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000000000
W
Reset0000000000000000
Table 47. Peripheral Status Registers 0…4 (ME_PS0…4) Field Descriptions
Field Description
S_<periph>
Peripheral status — These bits specify the current status of the peripherals in the system. If no
peripheral is mapped on a particular position (i.e., the corresponding MODS bit is ‘0’), the
corresponding bit is always read as ‘0’.
0 Peripheral is frozen
1 Peripheral is active