Reset Generation Module (MC_RGM) RM0046
200/936 Doc ID 16912 Rev 5
Note: This register is reset on any enabled ‘destructive’ or ‘functional’ reset event.
Functional Bidirectional Reset Enable Register (RGM_FBRE)
This register enables the generation of an external reset on functional reset. It can be
accessed in read/write in either supervisor mode or test mode. It can be accessed in read in
user mode.
SS_PLL0
Short Sequence for PLL0 fail
0 The reset sequence triggered by a PLL0 fail event will start from PHASE1
1 The reset sequence triggered by a PLL0 fail event will start from PHASE3, skipping PHASE1
and PHASE2
SS_CHKSTOP
Short Sequence for checkstop reset
0 The reset sequence triggered by a checkstop reset event will start from PHASE1
SS_SOFT
Short Sequence for software reset
0 The reset sequence triggered by a software reset event will start from PHASE1
SS_CORE
Short Sequence for core reset
0 The reset sequence triggered by a core reset event will start from PHASE1
1 The reset sequence triggered by a core reset event will start from PHASE3, skipping PHASE1
and PHASE2
SS_JTAG
Short Sequence for JTAG initiated reset
0 The reset sequence triggered by a JTAG initiated reset event will start from PHASE1
1 The reset sequence triggered by a JTAG initiated reset event will start from PHASE3, skipping
PHASE1 and PHASE2
Table 63. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions
Field Description
Figure 75. Functional Bidirectional Reset Enable Register (RGM_FBRE)
Address 0xC3FE_401C Access: User read, Supervisor read/write, Test read/write
0123456789101112131415
R
BE_EXR
00000
BE_PLL1
BE_FLASH
BE_LVD45
BE_CMU0_FHL
BE_CMU0_OLR
BE_PLL0
BE_CHKSTOP
BE_SOFT
BE_CORE
BE_JTAG
W
POR0000000000000000
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