ST SPC560P34 - Table 70. INTC_CPR Field Descriptions

Interrupt Controller (INTC) RM0046
214/936 Doc ID 16912 Rev 5
The INTC_CPR masks any peripheral or software settable interrupt request set at the same
or lower priority as the current value of the INTC_CPR[PRI] field from generating an
interrupt request to the processor. When the INTC interrupt acknowledge register
(INTC_IACKR) is read in software vector mode or the interrupt acknowledge signal from the
processor is asserted in hardware vector mode, the value of PRI is pushed onto the LIFO,
and PRI is updated with the priority of the preempting interrupt request. When the INTC
end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the INTC_CPR’s
PRI field.
The masking priority can be raised or lowered by writing to the PRI field, supporting the
PCP. Refer to Section 9.7.5, “Priority ceiling protocol.
Note: A store to modify the PRI field that closely precedes or follows an access to a shared
resource can result in a non-coherent access to the resource. Refer to Section , “Ensuring
coherency, for example code to ensure coherency.
Table 70. INTC_CPR field descriptions
Field Description
28–31
PRI[0:3]
Priority
PRI is the priority of the currently executing ISR according to the following:
1111 Priority 15—highest priority
1110 Priority 14
1101 Priority 13
1100 Priority 12
1011 Priority 11
1010 Priority 10
1001 Priority 9
1000 Priority 8
0111 Priority 7
0110 Priority 6
0101 Priority 5
0100 Priority 4
0011 Priority 3
0010 Priority 2
0001 Priority 1
0000 Priority 0—lowest priority