RM0046 DMA Channel Mux (DMA_MUX)
Doc ID 16912 Rev 5 425/936
19.1.3 Modes of operation
The following operation modes are available:
● Disabled Mode
In this mode, the DMA channel is disabled. Since disabling and enabling of DMA
channels is done primarily via the DMA configuration registers, this mode is used
mainly as the reset state for a DMA channel in the DMA Channel Mux. It may also be
used to temporarily suspend a DMA channel while reconfiguration of the system takes
place (for example, changing the period of a DMA trigger).
● Normal Mode
In this mode, a DMA source (such as DSPI_0_TX or DSPI_0_RX example) is routed
directly to the specified DMA channel. The operation of the DMA Mux in this mode is
completely transparent to the system.
● Periodic Trigger Mode
In this mode, a DMA source may only request a DMA transfer (such as when a transmit
buffer becomes empty or a receive buffer becomes full) periodically. Configuration of
the period is done in the registers of the Periodic Interrupt Timer (PIT).
DMA channels 0–3 may be used in all the modes listed above but channels 4–15 may be
configured only to disabled or normal mode.
19.2 External signal description
19.2.1 Overview
The DMA Mux has no external pins.
19.3 Memory map and register definition
This section provides a detailed description of all memory-mapped registers in the DMA
Mux.
19.3.1 Memory map
Table 200 shows the memory map for the DMA Mux. Note that all addresses are offsets; the
absolute address may be computed by adding the specified offset to the base address of
the DMA Mux.
Table 200. DMA_MUX memory map
Offset from
DMA_MUX_BASE
(0xFFFD_C000)
Register Location
0x0000 Channel #0 Configuration (CHCONFIG0) on page 19-427
0x0001 Channel #1 Configuration (CHCONFIG1) on page 19-427
0x0002 Channel #2 Configuration (CHCONFIG2) on page 19-427
0x0003 Channel #3 Configuration (CHCONFIG3) on page 19-427
0x0004 Channel #4 Configuration (CHCONFIG4) on page 19-427
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