Enhanced Direct Memory Access (eDMA) RM0046
406/936 Doc ID 16912 Rev 5
18.6 Functional description
This section provides an overview of the microarchitecture and functional operation of the
eDMA module.
18.6.1 eDMA microarchitecture
The eDMA module is partitioned into two major modules: the eDMA engine and the transfer
control descriptor local memory. Additionally, the eDMA engine is further partitioned into four
submodules, as shown in the following list:
● eDMA engine
– Address path: This module implements registered versions of two channel transfer
control descriptors: channel ‘x’ and channel ‘y,’ and is responsible for all the master
bus address calculations. All the implemented channels provide the exact same
functionality. This hardware structure allows the data transfers associated with one
channel to be preempted after the completion of a read/write sequence if a higher
priority channel service request is asserted while the first channel is active. After a
channel is activated, it runs until the minor loop is completed unless preempted by
a higher priority channel. This capability provides a mechanism (optionally
enabled by EDMA_CPRn[ECP]) where a large data move operation can be
preempted to minimize the time another channel is blocked from execution.
When any other channel is activated, the contents of its transfer control descriptor
is read from the local memory and loaded into the registers of the other address
path channel{x,y}. After the inner minor loop completes execution, the address
path hardware writes the new values for the TCDn.{SADDR, DADDR, CITER}
253
0x1C [29]
INT_HALF
Enable an interrupt when major counter is half complete.
If this flag is set, the channel generates an interrupt request by setting the bit in the
EDMA_ERQL when the current major iteration count reaches the halfway point.
The eDMA engine performs the compare (CITER == (BITER >> 1)). This halfway
point interrupt request supports double-buffered (aka ping-pong) schemes, or
where the processor needs an early indication of the data transfer’s progress
during data movement. CITER = BITER = 1 with INT_HALF enabled generates an
interrupt as it satisfies the equation (CITER == (BITER >> 1)) after a single
activation.
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
254
0x1C [30]
INT_MAJ
Enable an interrupt when major iteration count completes. If this flag is set, the
channel generates an interrupt request by setting the appropriate bit in the
EDMA_ERQL when the current major iteration count reaches zero.
0 The end-of-major loop interrupt is disabled.
1 The end-of-major loop interrupt is enabled.
255
0x1C [31]
START
Channel start. If this flag is set, the channel is requesting service. The eDMA
hardware automatically clears this flag after the channel begins execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software initiated service request.
Table 193. TCDn field descriptions (continued)
Bits
Word Offset
[n:n]
Field Name Description
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