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ST SPC560P34 - Table 294. ADC Digital Registers

ST SPC560P34
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RM0046 Analog-to-Digital Converter (ADC)
Doc ID 16912 Rev 5 587/936
Table 294. ADC digital registers
Offset from base
address
0xFFE0_0000
Register name Location
0x0000 Main Configuration Register (MCR) on page 23-588
0x0004 Main Status Register (MSR) on page 23-590
0x0008–0x000F Reserved
0x0010 Interrupt Status Register (ISR) on page 23-591
0x0014–0x001F Reserved
0x0020 Interrupt Mask Register (IMR) on page 23-592
0x0024–0x002F Reserved
0x0030 Watchdog Threshold Interrupt Status Register (WTISR) on page 23-593
0x0034 Watchdog Threshold Interrupt Mask Register (WTIMR) on page 23-594
0x0038–0x003F Reserved
0x0040 DMA Enable Register (DMAE) on page 23-595
0x0044 DMA Channel Select Register 0 (DMAR0) on page 23-596
0x0048–0x004F Reserved
0x0050 Threshold Control Register 0 (TRC0) on page 23-597
0x0054 Threshold Control Register 1 (TRC1) on page 23-597
0x0058 Threshold Control Register 2 (TRC2) on page 23-597
0x005C Threshold Control Register 3 (TRC3) on page 23-597
0x0060 Threshold Register 0 (THRHLR0) on page 23-598
0x0064 Threshold Register 1 (THRHLR1) on page 23-598
0x0068 Threshold Register 2 (THRHLR2) on page 23-598
0x006C Threshold Register 3 (THRHLR3) on page 23-598
0x0070–0x0093 Reserved
0x0094 Conversion Timing Register 0 (CTR0) on page 23-599
0x0098–0x00A3 Reserved
0x00A4 Normal Conversion Mask Register 0 (NCMR0) on page 23-599
0x00A8–0x00B3 Reserved
0x00B4 Injected Conversion Mask Register 0 (JCMR0) on page 23-600
0x00B8–00C7 Reserved
0x00C8 Power-down Exit Delay Register (PDEDR) on page 23-601
0x00CC–0x00FF
Reserved
0x0100 Channel 0 Data Register (CDR0) on page 23-601
0x0104 Channel 1 Data Register (CDR1) on page 23-601
0x0108 Channel 2 Data Register (CDR2) on page 23-601

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