RM0046 FlexPWM
Doc ID 16912 Rev 5 647/936
25.5 External signal descriptions
The PWM module has external pins named PWMA[n], PWMB[n], PWMX[n], FAULT[n],
EXT_SYNC. The PWM module also has on-chip inputs called EXT_CLK, EXT_FORCE and
on-chip outputs called OUT_TRIG[n].
25.5.1 PWMA[n] and PWMB[n] — external PWM pair
These pins are the output pins of the PWM channels. They can be independent PWM
signals or a complementary pair.
25.5.2 PWMX[n] — auxiliary PWM signal
These pins are the auxiliary output pins of the PWM channels. They can be independent
PWM signals. When not needed as an output, they can be used to generate the IPOL bit
during deadtime correction.
25.5.3 FAULT[n] — fault inputs
These are input pins for disabling selected PWM outputs.
25.5.4 EXT_SYNC — external synchronization signal
This input signal allows a source external to the PWM to initialize the PWM counter. In this
manner the PWM can be synchronized to external circuitry.
25.5.5 EXT_FORCE — external output force signal
This input signal allows a source external to the PWM to force an update of the PWM
outputs. In this manner the PWM can be synchronized to external circuitry. An example
would be to simultaneously switch all of the PWM outputs on a commutation boundary for
trapezoidal control of a BLDC motor. The source of EXT_FORCE signal is eTimer_0
OFLAG.
25.5.6 OUT_TRIG0[n] and OUT_TRIG1[n] — output triggers
These outputs allow the PWM submodules to control timing of the ADC conversions. See
Section , “Output Trigger Control register (TCTRL) for a description of how to enable these
outputs and how the compare registers match up to the output triggers.
25.5.7 EXT_CLK — external clock signal
This on-chip input signal allows an on-chip source external to the PWM (typically a Timer) to
control the PWM clocking. In this manner the PWM can be synchronized to the Timer. This
signal must be generated synchronously to the PWM’s clock since it is not resynchronized in
the PWM.
To Next Page
Loading...
