RM0046 Flash Memory
Doc ID 16912 Rev 5 321/936
reg single_ecc_error;// single-bit correctable ECC indicator from
Flash array
} bk1_page_buffer;
For the general case, a temporary holding register is written at the completion of an error-
free Flash access and the valid bit asserted. Subsequent Flash accesses that “hit” the
buffer, that is, the current access address matches the address stored in the temporary
holding register, can be serviced in 0 AHB wait states as the stored read data is routed from
the temporary register back to the requesting bus master.
The contents of the holding register are invalidated by the falling edge transition of
bk1_fl_done and on any non-sequential access with a non-zero value on haddr[28:24] (to
support wait state emulation) in the same manner as the bank0 page buffers. Additionally,
the B1_Py_BFE register bit can be cleared by software to invalidate the contents of the
holding register.
As noted in Section 17.2.13, “Flash error response operation the temporary holding register
is not marked as valid if the Flash array access terminated with any type of transfer error.
However, the result is that Flash array accesses that are tagged with a single-bit correctable
ECC event are loaded into the temporary holding register and validated. Accordingly, one
special case needing software invalidation relates to holding register “hits” on Flash data
that was tagged with a single-bit ECC event. Depending on the specific hardware
configuration, the reporting of a single-bit ECC event may generate an ECC alert interrupt.
In order to prevent repeated ECC alert interrupts, the page buffers need to be invalidated by
software after the first notification of the single-bit ECC event.
The bank1 temporary holding register effectively operates like a single page buffer.
17.2.16 Read-While-Write functionality
The platform Flash controller supports various programmable responses for read accesses
while the Flash is busy performing a write (program) or erase operation. For all situations,
the platform Flash controller uses the state of the Flash array’s bkn_fl_done output to
determine if it is busy performing some type of high-voltage operation, namely, if
bkn_fl_done = 0, the array is busy.
Specifically, there are two 3-bit read-while-write (BKn_RWWC) control register fields that
define the platform Flash controller’s response to these types of access sequences. There
are five unique responses that are defined by the BKn_RWWC setting: one immediately
reports an error on an attempted read, and four settings that support various stall-while-
write capabilities. Consider the details of these settings.
● BKn_RWWC = 0b0xx
– For this mode, any attempted Flash read to a busy array is immediately terminated
with an AHB error response and the read is blocked in the controller and not seen
by the Flash array.
● BKn_RWWC = 0b111
– This defines the basic stall-while-write capability and represents the default reset
setting. For this mode, the platform Flash controller module stalls any read
reference until the Flash has completed its program/erase operation. If a read
access arrives while the array is busy or if a falling-edge on bkn_fl_done occurs
while a read is still in progress, the AHB data phase is stalled by negating
hready_out and saving the address and attributes into holding registers. Once the
array has completed its program/erase operation, the platform Flash controller
uses the saved address and attribute information to create a pseudo address
To Next Page
Loading...
