ST SPC560P34 - Table 43. Interrupt Mask Register (ME_IM) Field Descriptions; Figure 47. Interrupt Mask Register (ME_IM)

RM0046 Mode Entry Module (MC_ME)
Doc ID 16912 Rev 5 153/936
Interrupt Mask Register (ME_IM)
This register controls whether an event generates an interrupt or not.
Figure 47. Interrupt Mask Register (ME_IM)
Address 0xC3FD_C010 Access: User read, Supervisor read/write, Test read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000000000
M_ICONF
M_IMODE
M_SAFE
M_MTC
W
Reset0000000000000000
Table 43. Interrupt Mask Register (ME_IM) Field Descriptions
Field Description
M_ICONF
Invalid mode configuration interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
M_IMODE
Invalid mode interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
M_SAFE
SAFE mode interrupt mask
0 SAFE mode interrupt is masked
1 SAFE mode interrupt is enabled
M_MTC
Mode transition complete interrupt mask
0 Mode transition complete interrupt is masked
1 Mode transition complete interrupt is enabled