eTimer RM0046
720/936 Doc ID 16912 Rev 5
Table 376. STS field descriptions
Field Description
WDF
Watchdog Time-out Flag
This bit is set when the watchdog times out by counting down to zero. The watchdog must be
enabled for time-out to occur and channel 0 must be in quadrature decode count mode
(CNTMODE = 100). This bit is cleared by writing a 1 to this bit. This bit is used in channel 0 only.
RCF
Redundant Channel Flag
This bit is set when there is a miscompare between this channel’s OFLAG value and the OFLAG
value of the corresponding redundant channel. Corresponding channels are grouped together in
the following pairs: 0 and 1, 2 and 3, 4 and 5, or 6 and 7. This bit can only be set if the RDNT bit is
set. This bit is cleared by writing a 1 to this bit. This bit is used in even channels (0, 2, 4, and 6)
only.
ICF2
Input Capture 2 Flag
This bit is set when an input capture event (as defined by CPT2MODE) occurs while the counter is
enabled and the word count of the CAPT2 FIFO exceeds the value of the CFWM field. This bit is
cleared by writing a 1 to this bit if ICF2DE is clear (no DMA) or it is cleared automatically by the
DMA access if ICF2DE is set (DMA).
ICF1
Input Capture 1 Flag
This bit is set when an input capture event (as defined by CPT1MODE) occurs while the counter is
enabled and the word count of the CAPT1 FIFO exceeds the value of the CFWM field. This bit is
cleared by writing a 1 to this bit if ICF1DE is clear (no DMA) or it is cleared automatically by the
DMA access if ICF1DE is set (DMA).
IEHF
Input Edge High Flag
This bit is set when a positive input transition occurs (on an input selected by SECSRC) while the
counter is enabled. This bit is cleared by writing a 1 to this bit.
IELF
Input Edge Low Flag
This bit is set when a negative input transition occurs (on an input selected by SECSRC) while the
counter is enabled. This bit is cleared by writing a 1 to this bit.
TOF
Timer Overflow Flag
This bit is set when the counter rolls over its maximum value 0xFFFF or 0x0000 (depending on
count direction). This bit is cleared by writing a 1 to this bit.
TCF2
Timer Compare 2 Flag
This bit is set when a successful compare occurs with COMP2. This bit is cleared by writing a 1 to
this bit.
TCF1
Timer Compare 1 Flag
This bit is set when a successful compare occurs with COMP1. This bit is cleared by writing a 1 to
this bit.
TCF
Timer Compare Flag
This bit is set when a successful compare occurs. This bit is cleared by writing a 1 to this bit.
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