ST SPC560P34 - Reset

RM0046 Functional Safety
Doc ID 16912 Rev 5 745/936
In the example in Figure 427, addresses 0x0C and 0x0D are unprotected. Therefore their
corresponding lock bits SLBR3.SLB[1:0] are always 0b0 (shown in bold). When doing a 32-
bit write access to address 0x200C only lock bits SLBR3.SLB[3:2] are set while bits
SLBR3.SLB[1:0] stay 0b0.
Note: Lock bits can only be set via writes to the mirror module space. Reads from the mirror
module space will not change the lock bits.
Write protection for locking bits
Changing the locking bits through any of the procedures mentioned in Section , “Change
lock settings directly via area #4, and Section , “Enable locking via mirror module space
(area #3) is only possible as long as the GCR[HLB] bit is cleared. Once this bit is set the
locking bits can no longer be modified until there was a system reset.
Access errors
The protection module generates transfer errors under several circumstances. For the area
definition refer to Figure 419.
1. If accessing area #1 or area #3, the protection module will pass on any access error
from the underlying Module under Protection.
– If user mode is not allowed, user writes to all areas will assert a transfer error and
the writes will be blocked.
– If accessing the reserved area #2, a transfer error will be asserted.
– If accessing unimplemented 32-bit registers in area #4 and area #5 a transfer
error will be asserted.
– If writing to a register in area #1 and area #3 with Soft Lock Bit set for any of the
affected bytes a transfer error is asserted and the write will be blocked. Also the
complete write operation to non-protected bytes in this word is ignored.
– If writing to a Soft Lock Register in area #4 with the Hard Lock Bit being set a
transfer error is asserted.
– Any write operation in any access mode to area #3 while Hard Lock Bit GCR[HLB]
is set
27.2.7 Reset
The reset state of each individual bit is shown in Section , “Registers description. In
summary, after reset, locking for all MRn registers is disabled. The registers can be
accessed in Supervisor Mode only.
27.3 Software Watchdog Timer (SWT)
27.3.1 Overview
The Software Watchdog Timer (SWT) is a peripheral module that can prevent system
lockup in situations such as software getting trapped in a loop or if a bus transaction fails to
terminate. When enabled, the SWT requires periodic execution of a watchdog servicing
sequence. Writing the sequence resets the timer to a specified time-out period. If this
servicing action does not occur before the timer expires the SWT generates an interrupt or
hardware reset. The SWT can be configured to generate a reset or interrupt on an initial
time-out, a reset is always generated on a second consecutive time-out.