FlexPWM RM0046
686/936 Doc ID 16912 Rev 5
Figure 372. PWM generation hardware
The generation of the Local Sync signal is performed exactly the same way as the other
PWM signals in the submodule. While comparator 0 causes a rising edge of the Local Sync
signal, comparator 1 generates a falling edge. Comparator 1 is also hardwired to the reload
logic to generate the half cycle reload indicator.
If VAL1 is controlling the modulus of the counter and VAL0 is half of the VAL1 register minus
the INIT value, then the half cycle reload pulse will occur exactly half way through the timer
count period and the Local Sync will have a 50% duty cycle. On the other hand, if the VAL1
and VAL0 registers are not required for register reloading or counter initialization, they can
be used to modulate the duty cycle of the Local Sync signal effectively turning it into an
auxiliary PWM signal (PWMX) assuming that the PWMX pin is not being used for another
function such as deadtime distortion correction. Including the Local Sync signal, each
submodule is capable of generating three PWM signals where software has complete
control over each edge of each of the signals.
If the comparators and edge value registers are not required for PWM generation, they can
also be used for other functions such as output compares, generating output triggers, or
generating interrupts at timed intervals.
16-bit
comparator
16-bit
comparator
16-bit
comparator
16-bit
comparator
D
R
Q
PWMA_INIT
PWM on
PWM off
16-bit
comparator
16-bit
comparator
D
S
R
Q
PWMB_INIT
PWM on
PWM off
VAL0
VAL1
VAL2
VAL3
VAL4
VAL5
Output Triggers
Compare Interrupts
16-bit counter
R
Q
SYNC_INIT
PWM on
PWM off
D
S
S
Half Comp
Mod Comp
(inverted
PWMA
PWMB
PWMX
FORCE_OUT
FORCE_EN
Force Init
to Force Out
logic
Local Sync)
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