RM0046 FlexCAN
Doc ID 16912 Rev 5 573/936
Note: It must be guaranteed that the CPU only clears the bit causing the current interrupt. For this
reason, bit manipulation instructions (BSET) must not be used to clear interrupt flags. These
instructions may cause accidental clearing of interrupt flags that are set after entering the
current interrupt service routine.
If the Rx FIFO is enabled (bit FEN on MCR set), the interrupts corresponding to MBs 0 to 7
have a different behavior. Bit 7 of the IFLAG1 becomes the FIFO Overflow flag; bit 6
becomes the FIFO Warning flag, bit 5 becomes the Frames Available in FIFO flag and bits
4:0 are unused. See Section , “Interrupt Flags 1 Register (IFLAG1) for more information.
A combined interrupt for all MBs is also generated by an OR of all the interrupt sources from
MBs. This interrupt gets generated when any of the MBs generates an interrupt. In this case
the CPU must read the IFLAG Registers to determine which MB caused the interrupt.
The other five interrupt sources (Bus Off, Error, Tx Warning, Rx Warning, and Wakeup)
generate interrupts like the MB ones, and can be read from the ESR register. The Bus Off,
Error, Tx Warning, and Rx Warning interrupt mask bits are located in the CTRL register, and
the Wake-Up interrupt mask bit is located in the MCR.
22.4.11 Bus interface
The CPU access to FlexCAN registers is subject to the following rules:
● All reads and writes to test registers must be qualified with ips_test_access signal.
Read and write access to test mode registers in non test mode results in access error.
● Read and write access to supervisor registers in User Mode results in access error.
● Read and write access to unimplemented or reserved address space also results in
access error. Any access to unimplemented MB or Rx Individual Mask Register
locations results in access error. Any access to the Rx Individual Mask Register space
when the BCC bit in the MCR is negated results in access error.
● If MAXMB is programmed with a value smaller than the available number of MBs, then
the unused memory space can be used as general purpose RAM space. Note that the
Rx Individual Mask Registers can only be accessed in Freeze Mode, and this is still
true for unused space within this memory. Note also that reserved words within RAM
cannot be used. As an example, suppose FlexCAN is configured with 32 MBs and
MAXMB is programmed with 0. The maximum number of MBs in this case becomes 1.
The MB memory starts at 0x0060, but the space from 0x0060 to 0x007F is reserved
(for SMB usage), and the space from 0x0080 to 0x008F is used by the one MB. This
leaves us with the available space from 0x0090 to 0x027F. The available memory in the
Mask Registers space would be from 0x0884 to 0x08FF.
Note: Unused MB space must not be used as general purpose RAM while FlexCAN is transmitting
and receiving CAN frames.
22.5 Initialization/application information
This section provide instructions for initializing the FlexCAN module.
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