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Enhanced Direct Memory Access (eDMA) RM0046

390/936 Doc ID 16912 Rev 5

As a given channel completes the processing of its major iteration count, there is a flag in

the transfer control descriptor that can affect the ending state of the EDMA_ERQR bit for

that channel. If the TCD.D_REQ bit is set, then the corresponding EDMA_ERQR bit is

cleared after the major loop is complete, disabling the DMA hardware request. Otherwise if

the D_REQ bit is cleared, the state of the EDMA_ERQR bit is unaffected.

eDMA Enable Error Interrupt Register (EDMA_EEIRL)

The EDMA_EEIRL provides a bit map for the 16 channels to enable the error interrupt signal

for each channel. EDMA_EEIRL maps to channels 15-0.

The state of any given channel’s error interrupt enable is directly affected by writes to these

registers; it is also affected by writes to the EDMA_SEEIR and EDMA_CEEIR. The

EDMA_SEEIR and EDMA_CEEIR are provided so that the error interrupt enable for a single

channel can easily be modified without the need to perform a read-modify-write sequence to

the EDMA_EEIRL.

Both the DMA error indicator and this error interrupt enable flag must be asserted before an

error interrupt request for a given channel is asserted.

Figure 179. eDMA Enable Request Low Register (EDMA_ERQRL)

Address:

Base + 0x000C Access: User read/write

0123456789101112131415

R00000000 00000 000

Reset0000000000000000

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

ERQ

Reset0000000000000000

Table 178. EDMA_ERQRL field descriptions

Field Description

16–31

ERQn

Enable DMA hardware service request n.

0 The DMA request signal for channel n is disabled.

1 The DMA request signal for channel n is enabled.

ST SPC560P34 User Manual

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