ST SPC560P34 - Figure 158. Low;MID Address Space Block Select Register (LMS)

RM0046 Flash Memory
Doc ID 16912 Rev 5 351/936
Low/Mid Address Space Block Select register (LMS)
The Low/Mid Address Space Block Select register provides a means to select blocks to be
operated on during erase. Identical LMS registers are provided in the code Flash and the
data Flash blocks.
SLK[15:0]
16:31
Secondary Low Address Space Block Lock 15–0
These bits are used as an alternate means to lock the blocks of Low Address Space from program
and Erase.
For code Flash, SLK[5:0] are related to sectors B0F[5:0], respectively. See Table 1 4 2 for more
information.
For data Flash, SLK[3:0] are related to sectors B1F[3:0], respectively. See Ta ble 1 43 for more
information.
A value of 1 in a bit of the SLK register signifies that the corresponding block is locked for program
and Erase.
A value of 0 in a bit of the SLK register signifies that the corresponding block is available to receive
program and Erase pulses.
The SLK register is not writable once an interlock write is completed until MCR[DONE] is set at the
completion of the requested operation. Likewise, the SLK register is not writable if a high voltage
operation is suspended.
Upon reset, information from the TestFlash block is loaded into the SLK registers. The SLK bits
may be written as a register. Reset causes the bits to go back to their TestFlash block value. The
default value of the SLK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the SLK bits
default to locked, and are not writable. The reset value will always be 1 (independent of the
TestFlash block), and register writes will have no effect.
In the code Flash macrocell, bits SLK[15:6] are read-only and locked at 1.
.
In the data Flash macrocell, bits SLK[15:4] are read-only and locked at 1.
SLK is not writable unless SLE is high.
0 Low Address Space Block is unlocked and can be modified (if also LML[LLK] = 0).
1 Low Address Space Block is locked and cannot be modified.
1. This field is present only in SLL
Table 152. SLL and NVSLL field descriptions (continued)
Field Description
Figure 158. Low/Mid Address Space Block Select register (LMS)
Address: Base + 0x0010 Access: User read/write
0123456789101112131415
R00000000 00000 0 0 0
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
LSL
15
LSL
14
LSL
13
LSL
12
LSL
11
LSL
10
LSL
9
LSL
8
LSL
7
LSL
6
LSL
5
LSL
4
LSL
3
LSL
2
LSL
1
LSL
0
W
Reset0000000000000000