Nexus Development Interface (NDI) RM0046
904/936 Doc ID 16912 Rev 5
To signal the chip-level clock generator to re-enable m_clk, the p_wakeup output will be
asserted whenever the debug block is asserting a debug request to the CPU due to OCR
DR
being set, or jd_de_b assertion, and will remain set from then until the debug session ends
(jd_debug_b goes from asserted to negated). In addition, the status of the jd_mclk_on
input (after synchronization to the j_tclk clock domain) may be sampled along with other
status bits from the j_tdo output during the Shift_IR TAP controller state. This status may be
used if necessary by external debug firmware to ensure proper scan sequences occur to
registers in the m_clk clock domain.
Software Request During Normal Activity
Upon executing a ‘bkpt’ pseudo-instruction (for e200z0h, defined to be an all 0’s instruction
opcode) when the OCR register’s (FDB) bit is set (debug mode enable control bit is true),
and DBCR0
EDM
=1, the CPU enters the debug mode after the instruction following the ‘bkpt’
pseudo-instruction has entered the instruction register.
36.12.8 CPU Status and Control Scan Chain Register (CPUSCR)
A number of on-chip registers store the CPU pipeline status and are configured in a single
scan chain for access by the e200z0h OnCE controller. The CPUSCR register contains
these processor resources, which are used to restore the pipeline and resume normal chip
activity upon return from the debug mode, as well as a mechanism for the emulator software
to access processor and memory contents. Figure 519 shows the block diagram of the
pipeline information registers contained in the CPUSCR. Once debug mode has been
entered, it is required to scan in and update this register prior to exiting debug mode.
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