ST SPC560P34 - Figure 9. SPC560 P40;34 System Clock Generation

Clock Description RM0046
92/936 Doc ID 16912 Rev 5
Figure 9. SPC560P40/34 system clock generation
PHI_PCS
PHI
FMPLL_0
64 MHz
CMU_0
 1,  2,  3, ...  16
Clock Out Divider
MC_PLL Divider
CMU_PLL Divider
SP_PLL Divider
[0]
[2]
[4]
[5]
[8]
AUX Clock Selector 0
AUX Clock Selector 1
[0]
[2]
[4]
[5]
[8]
System Clock Selector 0
RC Oscillator
(IRC)
Oscillator
(XOSC40)
N.C.
IRC_CLK
16 MHz
SYS_CLK
64 MHz—50%
IRC_CLK
16 MHz
XOSC_CLK
8 MHz—50%
Clockout
30/32 MHz
 1,  2,  4,  8
Clock Out Selector
[0]
[1]
[2]
[3]
 1,  2,  3, ...  16
 1,  2,  3, ...  16
[0]
[2]
[4]
[5]
[8]
AUX Clock Selector 2
XOSC_CLK
8 MHz—50%
FMPLL_0_PCS_CLK
FMPLL_0_CLK
NOTE: FlexRay protocol clock does not support IRC as a clock source.
FMPLL_0_CLK
XOSC_CLK
IRC_CLK
FMPLL_0_PCS_CLK—64 MHz, 50%
FMPLL_0_CLK—64 MHz, 50%
SYS_CLK = System Clock
N.C.
N.C.
50%