RM0046 Fault Collection Unit (FCU)
Doc ID 16912 Rev 5 757/936
28.1.2 Features
The FCU includes the following features:
â—Ź Collection of critical faults
â—Ź Reporting of selected critical faults to external pins
● Fault flag status kept over non-destructive reset for later analysis (in a “Freeze” register)
â—Ź Continuous and synchronous latch of MC state
● MC state kept over non-destructive reset for later analysis (in a “Freeze” register)
â—Ź 4-state (Init, Normal, Alarm, Fault) finite state machine
â—Ź Different actions can be taken depending on fault type
â—Ź Selectable protocols for fault signal indication in Fault state (dual-rail, time-switching, bi-
stable)
â—Ź Programmable clock prescaler for time-switching output signal generation
â—Ź Protection mechanism to avoid unwanted clearing of fault flags
â—Ź Internal logic testing, by using a fake fault generator during initialization phase
28.1.3 Modes of operation
This section describes the basic functional modes of the FCU module.
Normal mode
In Normal operation, the FCU captures all the faults in real time and processes them
according to the fault type and the configuration set by the user.
Test mode
Test mode provides a testing mechanism of the FCU (for dormant fault detection). Test
mode can be entered during the configuration (Init) phase. The user can write to the Fake
Fault Generation Register (FCU_FFGR) and can check the behavior while staying in Test
mode. During Test mode, the state machine behaves normally. In Test mode, real faults are
not detected.
The user can inject fake faults by writing to the FCU_FFGR during Test mode to test the
peripheral. Fault flags are cleared when Test mode is exited. Asynchronous software faults
written to the FCU_FFGR during Init phase will not be latched. In order to test software
faults, the FCU_FFGR needs to be cleared during Init phase and written to during Normal
phase.
28.2 Memory map and register definition
The following sections define the FCU memory map, register layout and functionality.
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