ST SPC560P34 User Manual

RM0046 Interrupt Controller (INTC)
Doc ID 16912 Rev 5 235/936
An ISR whose PRIn in INTC Priority Select Registers (INTC_PSR0_3–INTC_PSR220_221)
has a value of 0 will not cause an interrupt request to the processor, even if its peripheral or
software settable interrupt request is asserted. For a peripheral interrupt request, not setting
its enable bit or disabling the mask bit will cause it to remain negated, which consequently
also will not cause an interrupt request to the processor. Since the ISRs are outside the
control of the RTOS, this ISR will not run unless called by another ISR or the interrupt
exception handler, perhaps after executing another ISR.
9.7.4 Order of execution
An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the
unique vectors associated with each of their peripheral or software configurable interrupt
requests. However, if multiple peripheral or software configurable interrupt requests are
asserted, more than one has the highest priority, and that priority is high enough to cause
preemption, the INTC selects the one with the lowest unique vector regardless of the order
in time that they asserted. However, the ability to meet deadlines with this scheduling
scheme is no less than if the ISRs execute in the time order that their peripheral or software
configurable interrupt requests asserted.
The example in Table 7 6 shows the order of execution of both ISRs with different priorities
and the same priority
Table 76. Order of ISR execution example
Step
#
Step Description
Code Executing at End of Step
PRI in
INTC_CPR
at End of
Step
RTOS
ISR108
(1)
ISR20
8
ISR30
8
ISR40
8
Interrupt
Exception
Handler
1 RTOS at priority 0 is executing. X 0
2
Peripheral interrupt request 100 at
priority 1 asserts. Interrupt taken.
X1
3
Peripheral interrupt request 400 at
priority 4 is asserts. Interrupt taken.
X4
4
Peripheral interrupt request 300 at
priority 3 is asserts.
X4
5
Peripheral interrupt request 200 at
priority 3 is asserts.
X4
6
ISR408 completes. Interrupt
exception handler writes to
INTC_EOIR.
X1
7
Interrupt taken. ISR208 starts to
execute, even though peripheral
interrupt request 300 asserted first.
X3
8
ISR208 completes. Interrupt
exception handler writes to
INTC_EOIR.
X1
9
Interrupt taken. ISR308 starts to
execute.
X3

ST SPC560P34 Specifications

General

Brand	ST
Model	SPC560P34
Category	Microcontrollers
Language	English