ST SPC560P34 - System Status and Configuration Module (SSCM); System Clocks and Clock Generation; Frequency-Modulated Phase-Locked Loop (FMPLL)

RM0046 Introduction
Doc ID 16912 Rev 5 57/936
● Ability to modify the ISR or task priority: modifying the priority can be used to
implement the priority ceiling protocol for accessing shared resources.
● 1 external high priority interrupt (NMI) directly accessing the main core and I/O
processor (IOP) critical interrupt mechanism
1.6.7 System status and configuration module (SSCM)
The system status and configuration module (SSCM) provides central device functionality.
The SSCM includes these features:
● System configuration and status
– Memory sizes/status
– Device mode and security status
– Determine boot vector
– Search code flash for bootable sector
–DMA status
● Debug status port enable and selection
● Bus and peripheral abort enable/disable
1.6.8 System clocks and clock generation
The following list summarizes the system clock and clock generation on the SPC560P40/34:
● Lock detect circuitry continuously monitors lock status
● Loss of clock (LOC) detection for PLL outputs
● Programmable output clock divider (1, 2, 4, 8)
● FlexPWM module and eTimer module running at the same frequency as the e200z0h
core
● Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency
trimming by user application
1.6.9 Frequency-modulated phase-locked loop (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input
clock. Further, the FMPLL supports programmable frequency modulation of the system
clock. The PLL multiplication factor, output clock divider ratio are all software configurable.
The FMPLL has the following major features:
● Input clock frequency: 4–40 MHz
● Maximum output frequency: 64 MHz
● Voltage controlled oscillator (VCO)—frequency 256–512 MHz
● Reduced frequency divider (RFD) for reduced frequency operation without forcing the
FMPLL to relock
● Frequency-modulated PLL
– Modulation enabled/disabled through software
– Triangle wave modulation
● Programmable modulation depth (±0.25% to ±4% deviation from center frequency):
programmable modulation frequency dependent on reference frequency
● Self-clocked mode (SCM) operation