RM0046 FlexPWM
Doc ID 16912 Rev 5 687/936
The 16-bit comparators shown in Figure 372 are “equal to or greater than” not just “equal to”
comparators. In addition, if both the set and reset of the flip-flop are both asserted, then the
flop output goes to 0.
25.8.5 Output compare capabilities
By using the VALx registers in conjunction with the submodule timer and 16-bit
comparators, buffered output compare functionality can be achieved with no additional
hardware required. Specifically, the following output compare functions are possible:
● An output compare sets the output high
● An output compare sets the output low
● An output compare generates an interrupt
● An output compare generates an output trigger
Referring again to Figure 372, an output compare is initiated by programming a VALx
register for a timer compare, which in turn causes the output of the D flip-flop to either set or
reset. For example, if an output compare is desired on the PWMA signal that sets it high,
VAL2 would be programmed with the counter value where the output compare should take
place. However, to prevent the D flip-flop from being reset again after the compare has
occurred, the VAL3 register must be programmed to a value outside of the modulus range of
the counter. Therefore, a compare that would result in resetting the D flip-flop output would
never occur. Conversely, if an output compare is desired on the PWMA signal that sets it
low, the VAL3 register is programmed with the appropriate count value and the VAL2
register is programmed with a value outside the counter modulus range. Regardless of
whether a high compare or low compare is programmed, an interrupt or output trigger can
be generated when the compare event occurs.
25.8.6 Force out logic
For each submodule software can select between seven signal sources for the
FORCE_OUT signal: the local FORCE bit, the Master Force signal from submodule 0, the
local Reload signal, the Master Reload signal from submodule 0, the Local Sync signal, the
Master Sync signal from submodule 0, or the EXT_FORCE signal from on or off chip
depending on the device architecture. The local signals are used when the user wants to
change the signals on the output pins of the submodule without regard for synchronization
with other submodules. However, if it is required that all signals on all submodule outputs
change at the same time, the Master signals or EXT_FORCE signal should be selected.
Figure 373 illustrates the Force logic. The SELA and SELB fields each choose from one of
four signals that can be supplied to the submodule outputs: the PWM signal, the inverted
PWM signal, a binary level specified by software via the OUTA and OUTB bits. The
selection can be determined ahead of time and, when a FORCE_OUT event occurs, these
values are presented to the signal selection mux, which immediately switches the requested
signal to the output of the mux for further processing downstream.
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