ST SPC560P34 - Figure 473. CRC Configuration Register (CRC_CFG); Table 430. CRC_CFG Field Descriptions

Cyclic Redundancy Check (CRC) RM0046
800/936 Doc ID 16912 Rev 5
32.5.1 CRC Configuration Register (CRC_CFG)
0x0010 CRC_CFG—CRC Configuration Register, Context 2 on page 32-800
0x0014 CRC_INP—CRC Input Register, Context 2 on page 32-801
0x0018 CRC_CSTAT—CRC Current Status Register, Context 2 on page 32-802
0x001C CRC_OUTP—CRC Output Register, Context 2 on page 32-802
0x0020–0x3FFF Reserved
Table 429. CRC memory map (continued)
Offset from
CRC_BASE
0xFFE6_8000
Register Location
Figure 473. CRC Configuration Register (CRC_CFG)
Address:
Context 1: Base + 0x0000
Context 2: Base + 0x0010
Access: User read/write
0123456789101112131415
R 00000 00000000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000 00000
POLYG
SWAP
INV
W
Reset0000000000000000
Table 430. CRC_CFG field descriptions
Field Description
0:28
Reserved
These are reserved bits. These bits are always read as 0 and must always be written with 0.
29
POLYG: Polynomial selection
0: CRC-CCITT polynomial.
1: CRC-32 polynomial.
This bit can be read and written by the software.
This bit can be written only during the configuration phase.