ST SPC560P34 - Table 38. MC

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Mode Entry Module (MC_ME) RM0046

142/936 Doc ID 16912 Rev 5

Table 38. MC_ME Memory Map

Address Name

0 1 2 3 4567891011 12 13 14 15

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

0xC3FD

_C000

ME_GS R S_CURRENT_MODE

S_MTRANS

100

S_PDO

S_MVR

S_DFLA S_CFLA

R0 0 0 0 00000

S_PLL0

S_XOSC0

S_16 MHz_IRC

S_SYSCLK

0xC3FD

_C004

ME_MCTL

TA R G ET_ MO D E

0000000 00000

R1 0 1 0 0101000 01111

W KEY

0xC3FD

_C008

ME_ME

R0 0 0 0 0000000 00000

R00000

STOP0

HALT0

RUN3

RUN2

RUN1

RUN0

DRUN

SAFE

TEST

RESET

0xC3FD

_C00C

ME_IS

R0 0 0 0 0000000 00000

R0 0 0 0 0000000 0

I_ICONF

I_IMODE

I_SAFE

I_MTC

W w1c w1c w1c w1c

0xC3FD

_C010

ME_IM

R0 0 0 0 0000000 00000

R0 0 0 0 0000000 0

M_ICONF

M_IMODE

M_SAFE

M_MTC

0xC3FD

_C014

ME_IMTS

R0 0 0 0 0000000 00000

R0 0 0 0 0000000

S_MTI

S_MRI

S_DMA

S_NMA

S_SEA

W w1c w1c w1c w1c w1c

Main Page

Default Chapter2
- Table of Contents2
Preface45
- Overview45
- Audience45
- Chapter Organization and Device-Specific Information45
- References45
Introduction46
- The SPC560P40/34 Microcontroller Family46
- Target Applications47
  - Application Examples47
  - Figure 1. Electric Power Steering Application47
- Features48
- Table 1. SPC560P40/34 Device Comparison48
- Figure 2. Airbag Application48
- Table 2. SPC560P40 Device Configuration Differences50
- Figure 3. Block Diagram (SPC560P40 Full-Featured Configuration)51
- Critical Performance Parameters52
- Chip-Level Features52
- Module Features53
- Developer Environment67
- Package67
SPC560P40/34 Memory Map69
- Table 3. Memory Map69
Signal Description72
- 100-Pin LQFP Pinout72
- Figure 4. 100-Pin LQFP Pinout - Full Featured Configuration (Top View)72
- Figure 5. 100-Pin LQFP Pinout - Airbag Configuration (Top View)73
- 64-Pin LQFP Pinout74
- Figure 6. 64-Pin LQFP Pinout - Full Featured Configuration (Top View)74
- Pin Description75
- CTU / ADC / Flexpwm / Etimer Connections88
- Table 7. CTU / ADC / Flexpwm / Etimer Connections88
- Figure 8. CTU / ADC / Flexpwm / Etimer Connections88
Clock Description91
- Clock Architecture91
- Figure 9. SPC560P40/34 System Clock Generation92
- Figure 10. SPC560P40/34 System Clock Distribution Part a93
- Available Clock Domains94
- Alternate Module Clock Domains96
- Clock Behavior in STOP and HALT Mode97
- System Clock Functional Safety97
- IRC 16 Mhz Internal RC Oscillator (RC_CTL)98
- XOSC External Crystal Oscillator98
- Frequency Modulated Phase Locked Loop (FMPLL)100
- Clock Monitor Unit (CMU)108
Clock Generation Module (MC_CGM)116
- Overview116
- Figure 26. MC_CGM Block Diagram117
- Features118
- External Signal Description118
- Memory Map and Register Definition118
- Table 24. MC_CGM Register Description118
- Table 25. MC_CGM Memory Map119
- Register Descriptions123
- Functional Description131
- System Clock Generation131
- Auxiliary Clock Generation132
- Dividers Functional Description134
- Figure 40. MC_CGM Auxiliary Clock 2 Generation Overview134
- Output Clock Multiplexing135
- Output Clock Division Selection135
- Figure 41. MC_CGM Output Clock Multiplexer and PAD[22] Generation135
Mode Entry Module (MC_ME)136
- Introduction136
- External Signal Description139
- Memory Map and Register Definition139
- Functional Description168
Power Control Unit (MC_PCU)184
- Introduction184
- External Signal Description185
- Memory Map and Register Definition185
Reset Generation Module (MC_RGM)187
- Introduction187
- External Signal Description190
- Memory Map and Register Definition190
- Functional Description202
Interrupt Controller (INTC)208
- Introduction208
- Features208
- Table 67. Interrupt Sources Available209
- Block Diagram210
- Modes of Operation210
  - Normal Mode210
  - Figure 77. INTC Block Diagram210
- Memory Map and Registers Description212
- Functional Description220
- Initialization/Application Information232
System Status and Configuration Module (SSCM)240
- Introduction240
- Memory Map and Register Description241
- Functional Description247
- Initialization/Application Information247
  - Reset247
  - Table 88. PWCMPH/L Allowed Register Accesses247
System Integration Unit Lite (SIUL)248
- Introduction248
- Overview248
- Features249
  - Figure 96. System Integration Unit Lite Block Diagram249
  - Register Protection250
- External Signal Description250
  - Detailed Signal Descriptions250
  - Table 89. SIUL Signal Properties250
- Memory Map and Register Description251
- Functional Description267
- Pin Muxing269
E200Z0 and E200Z0H Core270
- Overview270
- Features270
- Core Registers and Programmer's Model275
- Instruction Summary278
- Figure 120. E200 User Mode Program Model278
Peripheral Bridge (PBRIDGE)279
- Introduction279
- Functional Description280
  - Access Support280
  - General Operation280
Crossbar Switch (XBAR)281
- Introduction281
- Block Diagram281
- Table 110. Device XBAR Switch Ports281
- Figure 122. XBAR Block Diagram281
- Overview282
- Features282
- Modes of Operation282
  - Normal Mode282
  - Debug Mode282
- Functional Description282
Error Correction Status Module (ECSM)286
- Introduction286
- Overview286
- Features286
- Memory Map and Registers Description286
Internal Static RAM (SRAM)308
- Introduction308
- SRAM Operating Mode308
- Module Memory Map308
- Register Descriptions308
- SRAM ECC Mechanism308
- Functional Description310
- Initialization and Application Information310
Flash Memory311
- Introduction311
- Platform Flash Controller311
- Flash Memory330
Enhanced Direct Memory Access (Edma)382
- Introduction382
- Overview382
- Figure 176. Edma Block Diagram382
- Features383
- Modes of Operation383
  - Normal Mode383
  - Debug Mode384
- Memory Map and Register Definition384
- Functional Description406
- Initialization / Application Information414
DMA Channel Mux (DMA_MUX)424
- Table 200. DMA_MUX Memory Map425
- Modes of Operation425
- Table 201. Chconfig#X Field Descriptions427
- Table 202. Channel and Trigger Enabling427
- Figure 200. Channel Configuration Registers (Chconfig#N)427
- Register Descriptions427
- Table 203. DMA Channel Mapping428
- DMA Request Mapping428
  - Functional Description429
  - Figure 201. DMA Mux Triggered Channels Diagram430
  - Figure 202. DMA Mux Channel Triggering: Normal Operation430
  - Figure 203. DMA Mux Channel Triggering: Ignored Trigger431
  - DMA Channels with no Triggering Capability432
    - Deserial Serial Peripheral Interface (DSPI)437
    - Figure 205. DSPI Block Diagram437
    - Figure 206. DSPI with Queues and Edma438
    - Overview438
    - Modes of Operation439
  - Figure 204. DMA Mux Channel 4-15 Block Diagram432
  - Master Mode440
  - Signal Names and Descriptions441
  - Table 204. Signal Properties441
  - Memory Map and Registers Description442
  - Table 205. DSPI Memory Map442
  - Registers Description443
  - Figure 207. DSPI Module Configuration Register (Dspix_Mcr)444
  - Table 206. Dspix_Mcr Field Descriptions444
  - Figure 208. DSPI Transfer Count Register (Dspix_Tcr)447
  - Table 207. Dspix_Tcr Field Descriptions447
  - Figure 209. DSPI Clock and Transfer Attributes Registers 0-7 (Dspix_Ctarn)448
  - Table 208. Dspix_Ctarn Field Descriptions448
  - Table 209. DSPI SCK Duty Cycle451
  - Table 210. DSPI Transfer Frame Size451
  - Table 211. DSPI PCS to SCK Delay Scaler452
  - Table 212. DSPI after SCK Delay Scaler452
  - Table 213. DSPI Delay after Transfer Scaler452
  - Figure 210. DSPI Status Register (Dspix_Sr)453
  - Table 214. DSPI Baud Rate Scaler453
  - Table 215. Dspix_Sr Field Descriptions453
  - Figure 211. DSPI DMA / Interrupt Request Select and Enable Register (Dspix_Rser)455
  - Table 216. Dspix_Rser Field Descriptions455
  - Figure 212. DSPI PUSH TX FIFO Register (Dspix_Pushr)457
  - Table 217. Dspix_Pushr Field Descriptions457
  - Figure 213. DSPI POP RX FIFO Register (Dspix_Popr)459
  - Figure 214. DSPI Transmit FIFO Register 0-4 (Dspix_Txfrn)459
  - Table 218. Dspix_Popr Field Descriptions459
  - Figure 215. DSPI Receive FIFO Registers 0-4 (Dspix_Rxfrn)460
  - Functional Description460
  - Table 219. Dspix_Txfrn Field Descriptions460
  - Table 220. Dspix_Rxfrn Field Description460
  - Figure 216. SPI Serial Protocol Overview461
  - Modes of Operation461
  - Start and Stop of DSPI Transfers462
  - Figure 217. DSPI Start and Stop State Diagram463
  - Serial Peripheral Interface (SPI) Configuration463
  - Table 221. State Transitions for Start and Stop of DSPI Transfers463
  - DSPI Baud Rate and Clock Delay Generation466
  - Figure 218. Communications Clock Prescalers and Scalers466
  - Table 222. Baud Rate Computation Example467
  - Table 223. CS to SCK Delay Computation Example467
  - Table 224. after SCK Delay Computation Example467
  - Figure 219. Peripheral Chip Select Strobe Timing468
  - Table 225. Delay after Transfer Computation Example468
  - Table 226. Peripheral Chip Select Strobe Assert Computation Example469
  - Table 227. Peripheral Chip Select Strobe Negate Computation Example469
  - Transfer Formats469
  - Figure 220. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 0, FMSZ = 8)470
  - Figure 221. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 1, FMSZ = 8)471
  - Table 228. Delayed Master Sample Point472
  - Figure 222. DSPI Modified Transfer Format (MTFE = 1, CPHA = 0, F SCK = F SYS / 4)473
  - Figure 223. DSPI Modified Transfer Format (MTFE = 1, CPHA = 1, F SCK = F SYS / 4)474
  - Figure 224. Example of Non-Continuous Format (CPHA = 1, CONT = 0)474
  - Figure 225. Example of Continuous Transfer (CPHA = 1, CONT = 1)475
  - Continuous Serial Communications Clock476
  - Figure 226. Polarity Switching between Frames476
  - Figure 227. Continuous SCK Timing Diagram (CONT = 0)477
  - Figure 228. Continuous SCK Timing Diagram (CONT = 1)477
  - Interrupts/Dma Requests478
  - Table 229. Interrupt and DMA Request Conditions478
  - Power Saving Features479
  - Initialization and Application Information480
  - Table 230. Baud Rate Values481
  - Delay Settings482
    - Table 231. Delay Values482
    - Figure 229. TX FIFO Pointers and Counter483
    - Introduction485
    - Features Common to LIN and UART486
  - Figure 230. LIN Topology Network487
  - Figure 231. Linflex Block Diagram487
- Fractional Baud Rate Generation487
- Table 232. Error Calculation for Programmed Baud Rates488
- Figure 232. Linflex Operating Modes489
- Figure 233. Linflex in Loop Back Mode490
- Test Modes490
- Table 233. Linflex Memory Map491
- Figure 234. Linflex in Self Test Mode491
- Memory Map and Registers Description491
- Figure 235. LIN Control Register 1 (LINCR1)492
- Table 234. LINCR1 Field Descriptions493
- Table 235. Checksum Bits Configuration494
- Table 236. LIN Master Break Length Selection494
- Table 237. Operating Mode Selection495
- Figure 236. LIN Interrupt Enable Register (LINIER)495
- Table 238. LINIER Field Descriptions496
- Figure 237. LIN Status Register (LINSR)497
- Table 239. LINSR Field Descriptions498
- Table 240. LINESR Field Descriptions500
- Figure 238. LIN Error Status Register (LINESR)500
- Figure 239. UART Mode Control Register (UARTCR)501
- Table 241. UARTCR Field Descriptions502
- Table 242. UARTSR Field Descriptions503
- Figure 240. UART Mode Status Register (UARTSR)503
- Table 243. LINTCSR Field Descriptions505
- Figure 241. LIN Timeout Control Status Register (LINTCSR)505
- Table 244. LINOCR Field Descriptions506
- Figure 242. LIN Output Compare Register (LINOCR)506
- Figure 243. LIN Timeout Control Register (LINTOCR)506
- Table 245. LINTOCR Field Descriptions507
- Table 246. LINFBRR Field Descriptions507
- Figure 244. LIN Fractional Baud Rate Register (LINFBRR)507
- Table 247. LINIBRR Field Descriptions508
- Table 248. Integer Baud Rate Selection508
- Figure 245. LIN Integer Baud Rate Register (LINIBRR)508
- Table 249. LINCFR Field Descriptions509
- Figure 246. LIN Checksum Field Register (LINCFR)509
- Figure 247. LIN Control Register 2 (LINCR2)509
- Table 250. LINCR2 Field Descriptions510
- Table 251. BIDR Field Descriptions511
- Figure 248. Buffer Identifier Register (BIDR)511
- Table 252. BDRL Field Descriptions512
- Figure 249. Buffer Data Register LSB (BDRL)512
- Figure 250. Buffer Data Register MSB (BDRM)512
- Table 253. BDRM Field Descriptions513
- Table 254. IFER Field Descriptions513
- Figure 251. Identifier Filter Enable Register (IFER)513
- Table 255. IFMI Field Descriptions514
- Figure 252. Identifier Filter Match Index (IFMI)514
- Figure 253. Identifier Filter Mode Register (IFMR)514
- Table 256. IFMR Field Descriptions515
- Table 257. IFMR[IFM] Configuration515
- Table 258. Ifcr2N Field Descriptions516
- Figure 254. Identifier Filter Control Register (Ifcr2N)516
- Table 259. Ifcr2N + 1 Field Descriptions517
- Figure 255. Identifier Filter Control Register (Ifcr2N + 1)517
- Figure 256. UART Mode 8-Bit Data Frame518
- Figure 257. UART Mode 9-Bit Data Frame518
- Functional Description518
- Table 260. Message Buffer519
- LIN Mode520
- Table 261. Filter to Interrupt Vector Correlation525
- Figure 258. Filter Configuration-Register Organization525
- Figure 259. Identifier Match Index526
- Figure 260. LIN Synch Field Measurement527
- Bit Timeout Counter528
- Table 262. Linflex Interrupt Control529
- Figure 261. Header and Response Timeout529
- Interrupts529
- Figure 262. Flexcan Block Diagram531
- Introduction531
- Flexcan Module Features532
- Modes of Operation533
- Table 263. Flexcan Signals534
- External Signal Description534
- Table 264. Flexcan Module Memory Map535
- Table 265. Flexcan Register Reset Status535
- Table 266. Message Buffer MB0 Memory Mapping536
- Message Buffer Structure536
- Table 267. Message Buffer Structure Field Description537
- Figure 263. Message Buffer Structure537
- Table 268. Message Buffer Code for Rx Buffers538
- Table 269. Message Buffer Code for Tx Buffers539
- Table 270. MB0-MB31 Addresses539
- Rx FIFO Structure540
- Table 271. ID Table 0 - 7541
- Figure 264. Rx FIFO Structure541
- Table 272. Rx FIFO Structure Field Description542
- Registers Description542
- Table 273. MCR Field Descriptions543
- Figure 265. Module Configuration Register (MCR)543
- Table 274. IDAM Coding546
- Figure 266. Control Register (CTRL)546
- Table 275. CTRL Field Descriptions547
- Table 276. TIMER Field Descriptions550
- Figure 267. Free Running Timer (TIMER)550
- Figure 268. Rx Global Mask Register (RXGMASK)550
- Table 277. RXGMASK Field Description551
- Table 278. RX14MASK Field Description551
- Figure 269. Rx Buffer 14 Mask Register (RX14MASK)551
- Table 279. RX15MASK Field Description552
- Figure 270. Rx Buffer 15 Mask Register (RX15MASK)552
- Figure 271. Error Counter Register (ECR)553
- Table 280. Error and Status Register (ESR) Field Description554
- Figure 272. Error and Status Register (ESR)554
- Table 281. Fault Confinement State556
- Figure 273. Interrupt Masks 1 Register (IMASK1)556
- Table 282. IMASK1 Field Descriptions557
- Table 283. IFLAG1 Field Descriptions557
- Figure 274. Interrupt Flags 1 Register (IFLAG1)557
- Figure 275. Rx Individual Mask Registers (RXIMR0-RXIMR31)558
- Table 284. RXIMR0-RXIMR31 Field Descriptions559
- Table 285. RXIMR0-RXIMR31 Addresses559
- Functional Description560
- Arbitration Process561
- Matching Process563
- Data Coherence564
- Rx FIFO566
- CAN Protocol Related Features567
- Figure 276. CAN Engine Clocking Scheme568
- Figure 277. Segments Within the Bit Time569
- Table 286. Time Segment Syntax570
- Table 287. CAN Standard Compliant Bit Time Segment Settings570
- Figure 278. Arbitration, Match, and Move Time Windows570
- Table 288. Minimum Ratio between Peripheral Clock Frequency and CAN Bit Rate571
- Modes of Operation Details571
- Interrupts572
- Bus Interface573
- Flexcan Initialization Sequence574
  - Overview575
  - Figure 279. ADC Implementation Diagram576
  - Device-Specific Implementation576
  - Table 289. Configurations for Starting Normal Conversion577
  - Functional Description577
  - Figure 280. Normal Conversion Flow578
  - Figure 281. Injected Sample/Conversion Sequence579
  - Analog Clock Generator and Conversion Timings580
  - Figure 282. Prescaler Simplified Block Diagram581
  - ADC Sampling and Conversion Timing581
  - Table 290. ADC Sampling and Conversion Timing at 5 V / 3.3 V for ADC0582
  - Figure 283. Sampling and Conversion Timings582
  - Table 291. Max/Min Adc_Clk Frequency and Related Configuration Settings at 5 V / 3.3 V for ADC0583
  - ADC CTU (Cross Triggering Unit)583
  - Table 292. Values of Wdgxh and Wdgxl Fields584
  - Figure 284. Guarded Area584
  - Programmable Analog Watchdog584
  - Table 293. Example for Analog Watchdog Operation585
  - DMA Functionality585
  - Power-Down Mode586
  - Table 294. ADC Digital Registers587
  - Figure 285. Main Configuration Register (MCR)588
  - Control Logic Registers588
  - Table 295. MCR Field Descriptions589
  - Table 296. MSR Field Descriptions590
  - Figure 286. Main Status Register (MSR)590
  - Figure 287. Interrupt Status Register (ISR)591
  - Interrupt Registers591
  - Table 297. ISR Field Descriptions592
  - Table 298. IMR Field Descriptions592
  - Figure 288. Interrupt Mask Register (IMR)592
  - Table 299. WTISR Field Descriptions593
  - Figure 289. Channel Interrupt Mask Register 0 (CIMR0)593
  - Figure 290. Watchdog Threshold Interrupt Status Register (WTISR)593
  - Table 300. WTIMR Field Descriptions594
  - Figure 291. Watchdog Threshold Interrupt Mask Register (WTIMR)594
  - Table 301. DMAE Field Descriptions595
  - Figure 292. DMA Enable (DMAE) Register595
  - DMA Registers595
  - Table 302. Dmarx Field Descriptions596
  - Figure 293. DMA Channel Select Register 0 (DMAR0)596
  - Table 303. Trcx Field Descriptions597
  - Figure 294. Threshold Control Register (Trcx, X = [0597
  - Threshold Registers597
  - Table 304. Thrhlrx Field Descriptions598
  - Figure 295. Threshold Register (THRHLR[0:3])598
  - Table 305. CTR Field Descriptions599
  - Figure 296. Conversion Timing Registers CTR[0]599
  - Table 306. NCMR Field Descriptions600
  - Table 307. JCMR Field Descriptions600
  - Figure 297. Normal Conversion Mask Register 0 (NCMR0)600
  - Figure 298. Injected Conversion Mask Register 0 (JCMR0)600
  - Table 308. PDEDR Field Descriptions601
  - Figure 299. Power-Down Exit Delay Register (PDEDR)601
  - Delay Registers601
  - Table 309. CDR Field Descriptions602
  - Figure 300. Channel Data Registers (CDR[0602
  - Introduction603
  - Figure 301. Cross Triggering Unit Diagram604
  - Functional Description604
  - Figure 302. TGS in Triggered Mode605
  - Trigger Generator Subunit (TGS)605
  - Figure 303. Example Timing for TGS in Triggered Mode606
  - TGS in Sequential Mode606
  - Figure 304. TGS in Sequential Mode607
  - Figure 305. Example Timing for TGS in Sequential Mode607
  - TGS Counter607
  - Figure 306. TGS Counter Cases608
- Scheduler Subunit (SU)608
  - ADC Commands List610
  - Figure 307. Scheduler Subunit610
  - Table 310. ADC Commands Translation611
  - ADC Results612
- Reload Mechanism613
- Figure 308. Reload Error Scenario614
- Power Safety Mode614
- Interrupts and DMA Requests615
  - CTU Interrupt/Dma Requests616
  - Table 311. CTU Interrupts616
  - Table 312. CTU Memory Map617
  - Table 313. TGS Registers620
  - Table 314. SU Registers620
  - Table 315. CTU Registers620
  - Figure 309. Trigger Generator Sub-Unit Input Selection Register (TGSISR)621
  - Table 316. FIFO Registers621
  - Table 317. TGSISR Field Descriptions622
  - Figure 310. Trigger Generator Sub-Unit Control Register (TGSCR)624
  - Figure 311. Trigger X Compare Register (Txcr, X = 0624
  - Table 318. TGSCR Field Descriptions624
  - Figure 312. TGS Counter Compare Register (TGSCCR)625
  - Figure 313. TGS Counter Reload Register (TGSCRR)625
  - Table 319. Txcr Field Descriptions625
  - Table 320. TGSCCR Field Format625
  - Table 321. TGSCRR Field Descriptions625
  - Figure 314. Commands List Control Register 1 (CLCR1)626
  - Figure 315. Commands List Control Register 2 (CLCR2)626
  - Table 322. CLCR1 Field Descriptions626
  - Table 323. CLCR2 Field Descriptions626
  - Figure 316. Trigger Handler Control Register 1 (THCR1)627
  - Table 324. THCR1 Field Descriptions627
  - Figure 317. Trigger Handler Control Register 2 (THCR2)629
  - Table 325. THCR2 Field Descriptions629
  - Commands List Register X (X = 1,...,24) (Clrx)631
  - Figure 318. Commands List Register X (X = 1631
  - Figure 319. Commands List Register X (X = 1631
  - Table 326. Clrx (CMS = 0) Field Descriptions631
  - Figure 320. FIFO DMA Control Register (FDCR)632
  - Table 327. Clrx (CMS = 1) Field Descriptions632
  - Table 328. FDCR Field Descriptions632
  - Figure 321. FIFO Control Register (FCR)633
  - Table 329. FCR Field Descriptions633
  - Figure 322. FIFO Threshold Register (FTH)634
  - Table 330. FTH Field Descriptions634
  - Figure 323. FIFO Status Register (FST)635
  - Table 331. FST Field Descriptions635
  - FIFO Right Aligned Data X (X = 0,...,3) (Frx)636
  - Figure 324. FIFO Right Aligned Data X (X = 0636
  - FIFO Signed Left Aligned Data X (X = 0,...,3) (Flx)637
  - Figure 325. FIFO Signed Left Aligned Data X (X = 0637
  - Figure 326. Cross Triggering Unit Error Flag Register (CTUEFR)637
  - Table 332. Frx Field Descriptions637
  - Table 333. Flx Field Descriptions637
  - Figure 327. Cross Triggering Unit Interrupt Flag Register (CTUIFR)638
  - Table 334. CTUEFR Field Descriptions638
  - Figure 328. Cross Triggering Unit Interrupt/Dma Register (CTUIR)639
  - Table 335. CTUIFR Field Descriptions639
  - Figure 329. Control on Time Register (COTR)640
  - Table 336. CTUIR Field Descriptions640
  - Figure 330. Cross Triggering Unit Control Register (CTUCR)641
  - Table 337. COTR Field Descriptions641
  - Table 338. CTUCR Field Descriptions641
  - Figure 331. Cross Triggering Unit Digital Filter (CTUDF)642
  - Figure 332. Cross Triggering Unit Power Control Register (CTUPCR)642
  - Table 339. CTUDF Field Descriptions642
  - Table 340. CTUPCR Field Descriptions642
  - Overview643
  - Table 341. Modes When PWM Operation Is Restricted644
  - Figure 333. PWM Block Diagram645
- Block Diagrams645
  - Figure 334. PWM Submodule Block Diagram646
  - External Signal Descriptions647
  - Memory Map and Registers648
  - Table 342. Flexpwm Memory Map648
  - Register Descriptions650
  - Figure 335. Counter Register (CNT)651
  - Figure 336. Initial Count Register (INIT)651
  - Submodule Registers651
  - Figure 337. Control 2 Register (CTRL2)652
  - Table 343. CTRL2 Field Descriptions652
  - Figure 338. Control 1 Register (CTRL1)654
  - Table 344. CTRL1 Field Descriptions654
  - Table 345. PWM Reload Frequency655
  - Figure 339. Value Register 0 (VAL0)656
  - Table 346. PWM Prescaler656
  - Figure 340. Value Register 1 (VAL1)657
  - Figure 341. Value Register 2 (VAL2)657
  - Figure 342. Value Register 3 (VAL3)658
  - Figure 343. Value Register 4 (VAL4)658
  - Figure 344. Value Register 5 (VAL5)659
  - Figure 345. Output Control Register (OCTRL)659
  - Table 347. OCTRL Field Descriptions659
  - Figure 346. Status Register (STS)660
  - Figure 347. Interrupt Enable Register (INTEN)661
  - Table 348. STS Field Descriptions661
  - Figure 348. DMA Enable Register (DMAEN)662
  - Table 349. INTEN Field Descriptions662
  - Table 350. DMAEN Field Descriptions662
  - Figure 349. Output Trigger Control Register (TCTRL)663
  - Table 351. TCTRL Field Descriptions663
  - Figure 350. Fault Disable Mapping Register (DISMAP)664
  - Table 352. DISMAP Field Descriptions664
  - Configuration Registers665
  - Figure 351. Deadtime Count Register 0 (DTCNT0)665
  - Figure 352. Deadtime Count Register 1 (DTCNT1)665
  - Figure 353. Output Enable Register (OUTEN)665
  - Figure 354. Mask Register (MASK)666
  - Table 353. OUTEN Field Descriptions666
  - Table 354. MASK Field Descriptions666
  - Figure 355. Software Controlled Output Register (SWCOUT)667
  - Table 355. SWCOUT Field Descriptions667
  - Figure 356. Deadtime Source Select Register (DTSRCSEL)668
  - Table 356. DTSRCSEL Field Descriptions669
  - Figure 357. Master Control Register (MCTRL)670
  - Fault Channel Registers671
  - Figure 358. Fault Control Register (FCTRL)671
  - Table 357. MCTRL Field Descriptions671
  - Figure 359. Fault Status Register (FSTS)672
  - Table 358. FCTRL Field Descriptions672
  - Figure 360. Fault Filter Register (FFILT)673
  - Table 359. FSTS Field Descriptions673
  - Table 360. FFILT Field Descriptions673
  - Figure 361. Center-Aligned Example675
- Functional Description675
  - Edge-Aligned Pwms676
  - Figure 362. Edge-Aligned Example (INIT = VAL2 = VAL4)676
  - Figure 363. Phase-Shifted Outputs Example677
  - Double Switching Pwms678
  - Figure 364. Phase-Shifted Pwms Applied to a Transformer Primary678
  - ADC Triggering679
  - Figure 365. Double Switching Output Example679
  - Figure 366. Multiple Output Trigger Generation in Hardware680
  - Figure 367. Multiple Output Triggers over Several PWM Cycles681
  - Synchronous Switching of Multiple Outputs681
  - Figure 368. Sensorless BLDC Commutation Using the Force out Function682
- Functional Details682
  - Figure 369. Clocking Block Diagram for each PWM Submodule683
  - Counter Synchronization684
  - Figure 370. Register Reload Logic684
  - Figure 371. Submodule Timer Synchronization684
  - PWM Generation685
  - Figure 372. PWM Generation Hardware686
  - Output Compare Capabilities687
  - Figure 373. Force out Logic688
  - Independent or Complementary Channel Operation688
  - Deadtime Insertion Logic689
  - Figure 374. Complementary Channel Pair689
  - Figure 375. Typical 3-Phase AC Motor Drive689
  - Figure 376. Deadtime Insertion and Fine Control Logic690
  - Figure 377. Deadtime Insertion691
  - Top/Bottom Correction691
  - Figure 378. Deadtime Distortion692
  - Figure 379. Current-Status Sense Scheme for Deadtime Correction693
  - Manual Correction693
  - Figure 380. Output Voltage Waveforms694
  - Output Logic694
  - Fault Protection695
  - Figure 381. Output Logic Section695
  - Fault Pin Filter696
  - Figure 382. Fault Decoder for PWMA696
  - Table 361. Fault Mapping696
  - Figure 383. Automatic Fault Clearing697
  - Fault Testing698
  - Figure 384. Manual Fault Clearing (FSAFE = 0)698
  - Figure 385. Manual Fault Clearing (FSAFE = 1)698
  - Figure 386. Full Cycle Reload Frequency Change699
  - Figure 387. Half Cycle Reload Frequency Change699
  - Load Frequency699
  - Figure 388. Full and Half Cycle Reload Frequency Change700
  - Figure 389. PWMF Reload Interrupt Request700
  - Reload Flag700
  - Table 362. Interrupt Summary701
- Clocks701
  - Table 363. DMA Summary702
  - Etimer703
  - Features704
  - Figure 390. Etimer Block Diagram705
- Module Block Diagram705
  - Figure 391. Etimer Channel Block Diagram706
  - Table 364. Etimer Memory Map707
  - Figure 392. Compare Register 1 (COMP1)710
  - Timer Channel Registers710
  - Figure 393. Compare Register 2 (COMP2)711
  - Figure 394. Capture Register 1 (CAPT1)711
  - Table 365. COMP1 Field Descriptions711
  - Table 366. COMP2 Field Descriptions711
  - Figure 395. Capture Register 2 (CAPT2)712
  - Figure 396. Load Register (LOAD)712
  - Table 367. CAPT1 Field Descriptions712
  - Table 368. CAPT2 Field Descriptions712
  - Figure 397. Hold Register (HOLD)713
  - Figure 398. Counter Register (CNTR)713
  - Table 369. LOAD Field Descriptions713
  - Table 370. HOLD Field Descriptions713
  - Figure 399. Control Register 1 (CTRL1)714
  - Table 371. CNTR Field Descriptions714
  - Table 372. CTRL1 Field Descriptions714
  - Table 373. Count Source Values715
  - Figure 400. Control Register 2 (CTRL2)716
  - Table 374. CTRL2 Field Descriptions716
  - Figure 401. Control Register 3 (CTRL3)718
  - Figure 402. Status Register (STS)719
  - Table 375. CTRL3 Field Descriptions719
  - Table 376. STS Field Descriptions720
  - Figure 403. Interrupt and DMA Enable Register (INTDMA)721
  - Table 377. INTDMA Field Descriptions721
  - Figure 404. Comparator Load 1 (CMPLD1)722
  - Figure 405. Comparator Load 2 (CMPLD2)722
  - Table 378. CMPLD1 Field Descriptions722
  - Figure 406. Compare and Capture Control Register (CCCTRL)723
  - Table 379. CMPLD2 Field Descriptions723
  - Table 380. CCCTRL Field Descriptions723
  - Figure 407. Input Filter Register (FILT)725
  - Table 381. FILT Field Descriptions725
  - Watchdog Timer Registers725
  - Configuration Registers726
  - Figure 408. Watchdog Time-Out Low Word Register (WDTOL)726
  - Figure 409. Watchdog Time-Out High Word Register (WDTOH)726
  - Figure 410. Channel Enable Register (ENBL)726
  - Table 382. WDTOL, WDTOH Field Descriptions726
  - Figure 411. DMA Request 0 Select Register (DREQ0)727
  - Figure 412. DMA Request 1 Select Register (DREQ1)727
  - Table 383. ENBL Field Descriptions727
  - Table 384. Dreqn Field Descriptions728
  - Functional Description729
  - Figure 413. Quadrature Incremental Position Encoder730
  - Figure 414. Triggered Count Mode (Length = 1)731
  - Figure 415. One-Shot Mode (Length = 1)731
  - Figure 416. Pulse Output Mode732
  - Figure 417. Variable PWM Waveform733
  - Other Features734
- Clocks735
- Table 385. Interrupt Summary736
- Table 386. DMA Summary736
- Interrupts736
- Figure 418. Register Protection Module Block Diagram737
Functional Safety737
- Figure 419. Register Protection Memory Diagram738
- Features738
Wakeup Unit (WKPU)776
- Table 415. NSR Field Descriptions777
- Figure 453. NMI Status Flag Register (NSR)777
- Registers Description777
- Use Cases and Limitations803
- Figure 477. DMA-CRC Transmission Sequence804
- Figure 478. DMA-CRC Reception Sequence805
- Table 434. BAM Memory Organization806
Boot Assist Module (BAM)806
- Figure 479. Boot Mode Selection807
Voltage Regulators and Power Supplies836
- VREG Digital Interface837
- Table 452. VREG_CTL Field Descriptions838
- Figure 495. Voltage Regulator Control Register (VREG_CTL)838
- Registers Description838
- Table 453. VREG_STATUS Field Descriptions839
- Figure 496. Voltage Regulator Status Register (VREG_STATUS)839
- Power Supply Strategy839
- Figure 497. JTAG Controller Block Diagram841
IEEE 1149.1 Test Access Port Controller (JTAGC)841
- Features842
- Table 454. JTAG Signal Properties843
- External Signal Description843
- Debug Support Overview858
  - Hardware Debug Facilities859
  - Figure 505. E200Z0H Debug Resources861
- Software Debug Events and Exceptions861
- External Debug Support888
- Watchpoint Support910
- Basic Steps for Enabling, Using, and Exiting External Debug Mode911
- Functional Description912
- Table 473. JTAGC Instruction Opcodes to Enable Nexus Clients913
- Table 474. Nexus Client JTAG Instructions913
- Debug Mode Control913
- Table 475. Registers under Protection914
- Table 476. Revision History925
- Document Revision History925
- Figure 57. Peripheral Status Register 0 (ME_PS0)933

ST SPC560P34 - Table 38. MC_ME Memory Map

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