ST SPC560P34 - Figure 54. RUN0; Figure 55. HALT0 Mode Configuration Register (ME_HALT0_MC)

RM0046 Mode Entry Module (MC_ME)
Doc ID 16912 Rev 5 161/936
RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC)
This register configures system behavior during RUN0…3 modes. Please refer to Ta bl e 4 6
for details.
Note: Byte write accesses are not allowed to this register.
HALT0 Mode Configuration Register (ME_HALT0_MC)
Figure 54. RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC)
Address 0xC3FD_C030 - 0xC3FD_C03C Access: User read, Supervisor read/write, Test read/write
0123456789101112131415
R00000000PDO00
MVRON
DFLAON CFLAON
W
Reset0000000000011111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000000
PLL0ON
XOSC0ON
16 MHz_IRCON
SYSCLK
W
Reset0000000000010000
Figure 55. HALT0 Mode Configuration Register (ME_HALT0_MC)
Address 0xC3FD_C040 Access: User read, Supervisor read/write, Test read/write
0123456789101112131415
R00000000PDO00
MVRON
DFLAON CFLAON
W
Reset0000000000011010
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000000
PLL0ON
XOSC0ON
16 MHz_IRCON
SYSCLK
W
Reset0000000000010000