ST SPC560P34 - Figure 465. STM Control Register (STM_CR); Registers Description

RM0046 System Timer Module (STM)
Doc ID 16912 Rev 5 791/936
31.5.2 Registers description
The following sections detail the individual registers within the STM programming model.
STM Control Register (STM_CR)
The STM Control Register (STM_CR) includes the prescale value, freeze control and timer
enable bits.
0x0008–0x000F Reserved
0x0010 STM_CCR0—STM Channel 0 Control Register on page 31-793
0x0014 STM_CIR0—STM Channel 0 Interrupt Register on page 31-793
0x0018 STM_CMP0—STM Channel 0 Compare Register on page 31-794
0x001C Reserved
0x00200 STM_CCR1—STM Channel 1 Control Register on page 31-793
0x00244 STM_CIR1—STM Channel 1 Interrupt Register on page 31-793
0x00288 STM_CMP1—STM Channel 1 Compare Register on page 31-794
0x002C Reserved
0x0030 STM_CCR2—STM Channel 2 Control Register on page 31-793
0x0034 STM_CIR2—STM Channel 2 Interrupt Register on page 31-793
0x0038 STM_CMP2—STM Channel 2 Compare Register on page 31-794
0x003C Reserved
0x0040 STM_CCR3—STM Channel 3 Control Register on page 31-793
0x0044 STM_CIR3—STM Channel 3 Interrupt Register on page 31-793
0x0048 STM_CMP3—STM Channel 3 Compare Register on page 31-794
0x004C–0x3FFF Reserved
Table 423. STM memory map (continued)
Offset from
STM_BASE
0xFFF3_C000
Register Location
Figure 465. STM Control Register (STM_CR)
Address: Base + 0x0000 Access: User read/write
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CPS[7:0]
0 0 0000
FRZ TEN
W
Reset0000000000000000