ST SPC560P34 - Figure 508. DBCR1 Register

Nexus Development Interface (NDI) RM0046
872/936 Doc ID 16912 Rev 5
Debug Control Register 1 (DBCR1)
Debug Control Register 1 is used to configure Instruction Address Compare operation. The
DBCR1 register is shown in Figure 508
.
16 RET
Return Debug Event Enable
0 – RET debug events are disabled
1 – RET debug events are enabled
17:20 — Reserved
21 DEVT1
External Debug Event 1 Enable
0 – DEVT1 debug events are disabled
1 – DEVT1 debug events are enabled
22 DEVT2
External Debug Event 2 Enable
0 – DEVT2 debug events are disabled
1 – DEVT2 debug events are enabled
23:24 — Reserved
25 CIRPT
Critical Interrupt Taken Debug Event Enable
0 – CIRPT debug events are disabled
1 – CIRPT debug events are enabled
26 CRET
Critical Return Debug Event Enable
0 – CRET debug events are disabled
1 – CRET debug events are enabled
27:31 — Reserved
Table 459. DBCR0 Bit Definitions (continued)
Bit(s) Name Description
Figure 508. DBCR1 Register
SPR - 309;
0123456789101112131415
R
IAC1US IAC1ER IAC2US IAC2ER IAC12M
000000
W
Reset
(1)
0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IAC3US IAC3ER IAC4US IAC4ER IAC34M
000000
W
Reset0000000000000000
1. Reset by processor reset p_reset_b if DBCR0
EDM
=0, as well as unconditionally by m_por. If DBCR0
EDM
=1, DBERC0
masks off hardware-owned resources from reset by p_reset_b and only software-owned resources indicated by DBERC0
will be reset by p_reset_b.