RM0046 Mode Entry Module (MC_ME)
Doc ID 16912 Rev 5 177/936
Pad Switch-Off
If the PDO bit of the ME_<target mode>_MC register is ‘1’ then
● the outputs of the pads are forced to the high impedance state if the target mode is
SAFE or TEST
This step is executed only after the Peripheral Clocks Disable process has completed.
Clock Sources (with no Dependencies) Switch-Off
Based on the device mode and the <clock source>ON bits of the ME_<mode>_MC
registers, if a given clock source is to be switched off and no other clock source needs it to
be on, the MC_ME requests the clock source to power down and updates its availability
status bit S_<clock source> of the ME_GS register to ‘0’. The following clock sources
switched off at this step:
● the 4 MHz crystal oscillator
● the system PLL
This step is executed only after the System Clock Switching process has completed.
Clock Sources (with Dependencies) Switch-Off
Based on the device mode and the <clock source>ON bits of the ME_<mode>_MC
registers, if a given clock source is to be switched off and all clock sources which need this
clock source to be on have been switched off, the MC_ME requests the clock source to
power down and updates its availability status bit S_<clock source> of the ME_GS register
to ‘0’. The following clock sources switched off at this step:
● the 16 MHz internal RC oscillator
This step is executed only after
● the System Clock Switching process has completed in order not to lose the current
system clock during mode transition
● the Clock Sources (with no Dependencies) Switch-Off process has completed in order
to, for example, prevent unwanted lock transitions
Table 52. MC_ME System Clock Selection Overview
System
Clock
Source
Mode
RESET TEST SAFE DRUN RUN0…3 HALT0 STOP0
16 MHz
int. RC
osc.
(default)
(default)
(default)
(default)
(default)
(default)
(default)
4 MHz
crystal
osc.
system
PLL
system
clock is
disabled
1. disabling the system clock during TEST mode will require a reset in order to exit TEST mode
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