Mode Entry Module (MC_ME) RM0046
178/936 Doc ID 16912 Rev 5
Flash Switch-Off
Based on the CFLAON and DFLAON bit fields of the ME_<current mode>_MC and
ME_<target mode>_MC registers, if any of the flashes is to be put in its low-power or power-
down mode, the MC_ME requests the flash to enter the corresponding power mode and
waits for the flash to acknowledge. The exact power mode status of the flashes is updated in
the S_CFLA and S_DFLA bit fields of the ME_GS register. This step is executed only when
the Processor and System Memory Clock Disable process has completed.
Current Mode Update
The current mode status bit field S_CURRENT_MODE of the ME_GS register is updated
with the target mode bit field TARGET_MODE of the ME_MCTL register when:
● all the updated status bits in the ME_GS register match the configuration specified in
the ME_<target mode>_MC register
● power sequences are done
● clock disable/enable process is finished
● processor low-power mode (halt/stop) entry and exit processes are finished
Software can monitor the mode transition status by reading the S_MTRANS bit of the
ME_GS register. The mode transition latency can differ from one mode to another
depending on the resources’ availability before the new mode request and the target mode’s
requirements.
If a mode transition is taking longer to complete than is expected, the ME_DMTS register
can indicate which process is still in progress.
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