ST SPC560P34 - Power Saving Features

RM0046 Deserial Serial Peripheral Interface (DSPI)
Doc ID 16912 Rev 5 479/936
operating in slave mode and SPI configuration is empty, and a transfer is initiated from an
external SPI master. If the TFUF bit is set while the TFUF_RE bit in the DSPIx_RSER is set,
an interrupt request is generated.
Receive FIFO drain interrupt or DMA request (RFDF)
The receive FIFO drain request indicates that the RX FIFO is not empty. The receive FIFO
drain request is generated when the number of entries in the RX FIFO is not zero, and the
RFDF_RE bit in the DSPIx_RSER is set. The RFDF_DIRS bit in the DSPIx_RSER selects
whether a DMA request or an interrupt request is generated.
Receive FIFO overflow interrupt request (RFOF)
The receive FIFO overflow request indicates that an overflow condition in the RX FIFO has
occurred. A receive FIFO overflow request is generated when RX FIFO and shift register are
full and a transfer is initiated. The RFOF_RE bit in the DSPIx_RSER must be set for the
interrupt request to be generated.
Depending on the state of the ROOE bit in the DSPIx_MCR, the data from the transfer that
generated the overflow is either ignored or shifted in to the shift register. If the ROOE bit is
set, the incoming data is shifted in to the shift register. If the ROOE bit is negated, the
incoming data is ignored.
FIFO overrun request (TFUF) or (RFOF)
The FIFO overrun request indicates that at least one of the FIFOs in the DSPI has exceeded
its capacity. The FIFO overrun request is generated by logically OR’ing together the RX
FIFO overflow and TX FIFO underflow signals.
20.8.8 Power saving features
The DSPI supports two power-saving strategies:
● Module disable mode—clock gating of non-memory mapped logic
● Clock gating of slave interface signals and clock to memory-mapped logic
Module disable mode
Module disable mode is a module-specific mode that the DSPI can enter to save power.
Host software can initiate the module disable mode by writing a 1 to the MDIS bit in the
DSPIx_MCR.In module disable mode, the DSPI is in a dormant state, but the memory
mapped registers are still accessible. Certain read or write operations have a different affect
when the DSPI is in the module disable mode. Reading the RX FIFO pop register does not
change the state of the RX FIFO. Likewise, writing to the TX FIFO push register does not
change the state of the TX FIFO. Clearing either of the FIFOs does not have any effect in
the module disable mode. Changes to the DIS_TXF and DIS_RXF fields of the DSPIx_MCR
does not have any affect in the module disable mode. In the module disable mode, all status
bits and register flags in the DSPI return the correct values when read, but writing to them
has no affect. Writing to the DSPIx_TCR during module disable mode does not have an
effect. Interrupt and DMA request signals cannot be cleared while in the module disable
mode.