ST SPC560P34 - Figure 206. DSPI with Queues and Edma; Overview

Deserial Serial Peripheral Interface (DSPI) RM0046
438/936 Doc ID 16912 Rev 5
20.3 Overview
The register content is transmitted using an SPI protocol. There are three DSPI modules
(DSPI_0, DSPI_1, and DSPI_2) on the device. The modules are identical except that
DSPI_0 has four additional chip select (CS
) lines.
For queued operations, the SPI queues reside in internal SRAM that is external to the DSPI.
Data transfers between the queues and the DSPI FIFOs are accomplished through the use
of the eDMA controller or through host software.
Figure 206 shows a DSPI with external queues in internal SRAM.
Figure 206. DSPI with queues and eDMA
20.4 Features
Internal SRAM
TX queue
RX queue
Address/control
TX FIFO
DSPI
RX FIFO
RX data
TX data
TX data RX data
Shift register
eDMA controller
Address/control
or host CPU