RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 911/936
36.14 Basic Steps for Enabling, Using, and Exiting External Debug
Mode
The following steps show one possible scenario for a debugger wishing to use the external
debug facilities. This simplified flow is intended to illustrate basic operations, but does not
cover all potential methods in depth.
Enabling External Debug Mode and initializing Debug registers
● The debugger should ensure that the jd_en_once control signal is asserted in order to
enable OnCE operation
● Select the OCR and write a value to it in which OCR
DR
, OCR
WKUP
, are set to ‘1’. The
tap controller must step through the proper states as outlined earlier. This step will
place the CPU in a debug state in which it is halted and awaiting single-step commands
or a release to normal mode
● Scan out the value of the OSR to determine that the CPU clock is running and the CPU
has entered the Debug state. This can be done in conjunction with a Read of the
CPUSCR. The OSR is shifted out during the Shift_IR state. The CPUSCR will be
shifted out during the Shift_DR state. The debugger should save the scanned-out value
of CPUSCR for later restoration.
● Select the DBCR0 register and update it with the DBCR0
EDM
bit set
● Clear the DBSR status bits
● Write appropriate values to the DBCRx, IAC, DAC registers. Note that the initial write to
DBCR0 will only affect the EDM bit, so the remaining portion of the register must now
be initialized, keeping the EDM bit set
At this point the system is ready to commence debug operations. Depending on the desired
operation, different steps must occur.
● Optionally, set the OCR
I_DMDIS
and/or OCR
D_DMDIS
control bits to ensure that no TLB
misses will occur while performing the debug operations
● Optionally, ensure that the values entered into the MSR portion of the CPUSCR during
the following steps cause interrupt to be disabled (clearing MSR
EE
and MSR
CE
). This
will ensure that external interrupt sources do not cause single-step errors.
jd_watchpt[3] IAC4
Instruction Address Compare 4 watchpoint
Asserted whenever an IAC4 compare occurs regardless of being enabled
to set DBSR status
jd_watchpt[4] DAC1
(1)
Data Address Compare 1 watchpoint
Asserted whenever a DAC1 compare occurs regardless of being enabled
to set DBSR status
jd_watchpt[5] DAC2
(1)
Data Address Compare 2 watchpoint
Asserted whenever a DAC2 compare occurs regardless of being enabled
to set DBSR status
1. If the corresponding event is completely disabled in DBCR0, either load-type or store-type data accesses are allowed to
generate watchpoints, otherwise watchpoints are generated only for the enabled conditions.
Table 472. Watchpoint Output Signal Assignments (continued)
Signal Name Type Description
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