ST SPC560P34 - Nexus Development Interface (NDI); Cyclic Redundancy Check (CRC); IEEE 1149.1 JTAG Controller

Introduction RM0046
66/936 Doc ID 16912 Rev 5
It implements the following features:
● Double buffered trigger generation unit with up to 8 independent triggers generated
from external triggers
● Trigger generation unit configurable in sequential mode or in triggered mode
● Each trigger can be appropriately delayed to compensate the delay of external low
pass filter
● Double buffered global trigger unit allowing eTimer synchronization and/or ADC
command generation
● Double buffered ADC command list pointers to minimize ADC-trigger unit update
● Double buffered ADC conversion command list with up to 24 ADC commands
● Each trigger capable of generating consecutive commands
● ADC conversion command allows to control ADC channel, single or synchronous
sampling, independent result queue selection
1.6.28 Nexus Development Interface (NDI)
The NDI (Nexus Development Interface) block is compliant with Nexus Class 1 of the IEEE-
ISTO 5001-2003 standard. This development support is supplied for MCUs without requiring
external address and data pins for internal visibility. The NDI block is an integration of
several individual Nexus blocks that are selected to provide the development support
interface for this device. The NDI block interfaces to the host processor and internal busses
to provide development support as per the IEEE-ISTO 5001-2003 Nexus Class 1 standard.
The development support provided includes access to the MCU’s internal memory map and
access to the processor’s internal registers.
The NDI provides the following features:
● Configured via the IEEE 1149.1
● All Nexus port pins operate at V
DDIO
(no dedicated power supply)
● Nexus Class 1 supports Static debug
1.6.29 Cyclic redundancy check (CRC)
The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The
CRC module features:
● Support for CRC-16-CCITT (x25 protocol):
– x
16
+ x
12
+ x
5
+ 1
● Support for CRC-32 (Ethernet protocol):
– x
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+ x
8
+ x
7
+ x
5
+ x
4
+ x
2
+ x + 1
● Zero wait states for each write/read operations to the CRC_CFG and CRC_INP
registers at the maximum frequency
1.6.30 IEEE 1149.1 JTAG controller
The JTAG controller (JTAGC) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. All data
input to and output from the JTAGC block is communicated in serial format. The JTAGC
block is compliant with the IEEE standard.