ST SPC560P34 - Figure 354. Mask Register (MASK); Table 353. OUTEN Field Descriptions; Table 354. MASK Field Descriptions

FlexPWM RM0046
666/936 Doc ID 16912 Rev 5
Mask register (MASK)
The relationship between the fields of MASK and the submodules is as follows:
● MASKx[3] enables/disables submodule 3
● MASKx[2] enables/disables submodule 2
● MASKx[1] enables/disables submodule 1
● MASKx[0] enables/disables submodule 0
Table 353. OUTEN field descriptions
Field Description
4:7
PWMA_EN[3:0]
PWMA Output Enables
These bits enable the PWMA outputs of each submodule.
0 PWMA output disabled.
1 PWMA output enabled.
8:11
PWMB_EN[3:0]
PWMB Output Enables
These bits enable the PWMB outputs of each submodule.
0 PWMB output disabled.
1 PWMB output enabled.
12:15
PWMX_EN[3:0]
PWMX Output Enables
These bits enable the PWMX outputs of each submodule. These bits should be set to 0 (output
disabled) when a PWMX pin is being used for deadtime correction.
0 PWMX output disabled.
1 PWMX output enabled.
Figure 354. Mask register (MASK)
Address: Base + 0x0142 Access: User read/write
0123456789101112131415
R0000
MASKA[3:0] MASKB[3:0] MASKX[3:0]
W
Reset0000000000000000
Table 354. MASK field descriptions
Field Description
4:7
MASKA[3:0]
PWMA Masks
These bits mask the PWMA outputs of each submodule forcing the output to logic 0 prior to
consideration of the output polarity.
0 PWMA output normal.
1 PWMA output masked.