RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 857/936
36.7 Memory map and registers description
The NDI block contains no memory-mapped registers. Nexus registers are accessed by a
development tool via the JTAG port using a client-select value and a register index. OnCE
registers are accessed by loading the appropriate value in the RS[0:6] field of the OnCE
command register (OCMD) via the JTAG port.
36.8 Interrupts and Exceptions
The Power Architecture technology defines the mechanisms by which the e200z0h core
implements interrupts and exceptions. The document uses the terminology Interrupt as the
action in which the processor saves its old context and begins execution at a predetermined
interrupt handler address. Exceptions are referred to as events, which when enabled, will
cause the processor to take an interrupt. This section uses the same terminology.
The Power Architecture exception mechanism allows the processor to change to supervisor
state as a result of unusual conditions arising in the execution of instructions, and from
external signals, bus errors, or various internal conditions. When interrupts occur,
information about the state of the processor is saved to machine state save/restore registers
(SRR0/SRR1, CSRR0/CSRR1, or DSRR0/DSRR1) and the processor begins execution at
an address (interrupt vector) determined by the Interrupt Vector Prefix register (IVPR), and
one of the hardwired Interrupt Vector Offset values. Processing of instructions within the
interrupt handler begins in supervisor mode.
Multiple exception conditions can map to a single interrupt vector, and may be distinguished
by examining registers associated with the interrupt. The Exception Syndrome register
(ESR) is updated with information specific to the exception type when an interrupt occurs.
To prevent loss of state information, interrupt handlers must save the information stored in
the machine state save/restore registers, soon after the interrupt has been taken. Three sets
of these registers are implemented; SRR0 and SRR1 for non-critical interrupts, CSRR0 and
CSRR1 for critical interrupts, and DSRR0 and DSRR1 for debug interrupts (when the Debug
APU is enabled). Hardware supports nesting of critical interrupts within non-critical
interrupts, and debug interrupts within both critical and non-critical interrupts. It is up to the
interrupt handler to save necessary state information if interrupts of a given class are re-
enabled within the handler.
The following terms are used to describe the stages of exception processing:
● Recognition—Exception recognition occurs when the condition that can cause an
exception is identified by the processor. This is also referred to as an exception event.
● Taken—An interrupt is said to be taken when control of instruction execution is passed
to the interrupt handler; that is, the context is saved and the instruction at the
appropriate vector offset is fetched and the interrupt handler routine begins.
● Handling—Interrupt handling is performed by the software linked to the appropriate
vector offset. Interrupt handling is begun in supervisor mode.
Returning from an interrupt is performed by executing an
se_rfi, se_rfci, or se_rfdi
instruction to restore state information from the respective machine state save/restore
register pair.
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