ST SPC560P34 - Figure 50. RESET Mode Configuration Register (ME_RESET_MC); Figure 51. TEST Mode Configuration Register (ME_TEST_MC)

Mode Entry Module (MC_ME) RM0046
158/936 Doc ID 16912 Rev 5
RESET Mode Configuration Register (ME_RESET_MC)
This register configures system behavior during RESET mode. Please refer to Ta ble 4 6 for
details.
TEST Mode Configuration Register (ME_TEST_MC)
Figure 50. RESET Mode Configuration Register (ME_RESET_MC)
Address 0xC3FD_C020 Access: User read, Supervisor read/write, Test read/write
0123456789101112131415
R00000000PDO00
MVRON
DFLAON CFLAON
W
Reset0000000000011111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000000
PLL0ON
XOSC0ON
16 MHz_IRCON
SYSCLK
W
Reset0000000000010000
Figure 51. TEST Mode Configuration Register (ME_TEST_MC)
Address 0xC3FD_C024 Access: User read, Supervisor read/write, Test read/write
0123456789101112131415
R00000000
PDO
00
MVRON
DFLAON CFLAON
W
Reset0000000000011111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000000
PLL0ON
XOSC0ON
16 MHz_IRCON
SYSCLK
W
Reset0000000000010000