RM0046 IEEE 1149.1 Test Access Port Controller (JTAGC)
Doc ID 16912 Rev 5 853/936
35.10 Initialization/Application Information
The test logic is a static logic design, and TCK can be stopped in either a high or low state
without loss of data. However, the system clock is not synchronized to TCK internally. Any
mixed operation using both the test logic and the system functional logic requires external
synchronization.
To initialize the JTAGC module and enable access to registers, the following sequence is
required:
1. Place the JTAGC in reset through TAP controller state machine transitions controlled by
TMS
– Load the appropriate instruction for the test or action to be performed.
110 1111
Shared Nexus Control Register (SNC)
(only available on the e200z0 core)
111 0000 – 111 1001 General Purpose Register Selects [0:9]
111 1010 – 111 1011 Reserved
111 1100 Reserved
111 1101
LSRL Select
(factory test use only)
111 1110 Enable_OnCE
111 1111 Bypass
Table 457. e200z0 OnCE register addressing (continued)
RS[0:6] Register selected
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