ST SPC560P34 - On-Chip Voltage Regulator (VREG); Developer Environment; Package

RM0046 Introduction
Doc ID 16912 Rev 5 67/936
The JTAG controller provides the following features:
● IEEE test access port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)
● Selectable modes of operation include JTAGC/debug or normal system operation.
● 5-bit instruction register that supports the following IEEE 1149.1-2001 defined
instructions:
– BYPASS
– IDCODE
–EXTEST
–SAMPLE
– SAMPLE/PRELOAD
● 5-bit instruction register that supports the additional following public instructions:
– ACCESS_AUX_TAP_NPC
– ACCESS_AUX_TAP_ONCE
● 3 test data registers:
– Bypass register
– Boundary scan register (size parameterized to support a variety of boundary scan
chain lengths)
– Device identification register
● TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry
1.6.31 On-chip voltage regulator (VREG)
The on-chip voltage regulator module provides the following features:
● Uses external NPN (negative-positive-negative) transistor
● Regulates external 3.3 V/5.0 V down to 1.2 V for the core logic
● Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V
1.7 Developer environment
The following development support is available:
● Automotive Evaluation Boards (EVBs) featuring CAN, LIN interfaces, and more
● Compilers
● Debuggers
● JTAG and Nexus interfaces
● Autocode generation tools
● Initialization tools
1.8 Package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.