RM0046 Clock Description
Doc ID 16912 Rev 5 91/936
4 Clock Description
This chapter describes the clock architectural implementation for SPC560P40/34.
The following clock related modules are implemented on the SPC560P40/34:
â—Ź Clock, Reset, and Mode Handling
– Clock Generation Module (CGM) (see Chapter 5: Clock Generation Module
(MC_CGM))
– Reset Generation Module (RGM) (see Chapter 8: Reset Generation Module
(MC_RGM))
– Mode Entry Module (ME) (see Chapter 6: Mode Entry Module (MC_ME))
● High Frequency Oscillator (XOSC) (see Section 4.7, “XOSC external crystal oscillator)
● High Frequency RC Oscillator (IRC) (see Section 4.6, “IRC 16 MHz internal RC
oscillator (RC_CTL))
● FMPLL (FMPLL_0) (see Section 4.8, “Frequency Modulated Phase Locked Loop
(FMPLL))
● CMU (CMU_0) (see Section 4.9, “Clock Monitor Unit (CMU))
● Periodic Interrupt Timer (PIT) (see 30, “Periodic Interrupt Timer (PIT))
● System Timer Module (STM_0) (see 31, “System Timer Module (STM))
● Software Watchdog Timer (SWT_0) (see Section 27.3, “Software Watchdog Timer
(SWT))
4.1 Clock architecture
The system and peripheral clocks are generated from three sources:
● IRC—internal RC oscillator clock
● XOSC—oscillator clock
â—Ź FMPLL_0 clock output
The clock architecture is shown in Figure 9, Figure 10, and Figure 11.
The frequencies shown in Figure 9 represent only one possible setting.
Note: MC_PLL_CLK and SP_PLL_CLK are SYS_CLK.
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