ST SPC560P34 - Memory Map and Register Description; Table 17. CMU Memory Map

RM0046 Clock Description
Doc ID 16912 Rev 5 111/936
If F
SYS_CLK
is greater than a reference value determined by the
CMU_1_HFREFR_A[HFREF_A] bits and the system clock is enabled, then:
● CMU_1_ISR[FHHI] is set
● A failure event is signaled to the MC_RGM and FCU, which in turn can generate a
‘functional' reset, a SAFE mode request, or an interrupt
If F
SYS_CLK
is less than a reference clock frequency (F
IRCOSC_CLK
4) and the system clock
is enabled, then:
● CMU_1_ISR[FLCI] is set
● A failure event FLC is signaled to the MC_RGM and Fault Collection Unit, which in turn
can generate a ‘functional' reset, a SAFE mode request, or an interrupt
If F
SYS_CLK
is less than a reference value determined by the
CMU_1_LFREFR_A[LFREF_A] bits and the system clock is enabled, then:
● CMU_1_ISR[FLLI] is set
● A failure event is signaled to the MC_RGM and FCU, which in turn can generate a
‘functional’ reset, a SAFE mode request, or an interrupt
Note: The system clock monitor may produce a false event when F
SYS_CLK
is less than
2
 F
IRCOSC_CLK
/2
CMU_1_CSR[RCDIV]
due to an accuracy limitation of the compare circuitry.
Frequency meter
The frequency meter calibrates the internal RC oscillator (CK_IRC) using a known
frequency.
Note: This value can then be stored into the flash so that application software can reuse it later on.
The reference clock will be always the XOSC. A simple frequency meter returns a draft
value of CK_IRC. The measure starts when bit SFM (Start Frequency Measure) in the
CMU_CSR is set to ‘1’. The measurement duration is given by the CMU_MDR in numbers
of IRC clock cycles with a width of 20 bits. Bit SFM is reset to ‘0’ by hardware once the
frequency measurement is done and the count is loaded in the CMU_FDR. The frequency
f
RC
can be derived from the value loaded in the CMU_FDR as follows:
Equation 12
f
RC
= (f
OSC
× MD) / n
where n is the value in the CMU_FDR and MD is the value in the CMU_MDR.
4.9.4 Memory map and register description
Table 1 7 shows the memory map of the CMU.
Table 17. CMU memory map
Offset from
CMU_BASE
(0xC3FE_0100)
Register Access Reset value Location
0x0000 Control Status Register (CMU_0_CSR) R/W 0x0000_0006 on page 4-112
0x0004 Frequency Display Register (CMU_0_FDISP) R 0x0000_0000 on page 4-113
0x0008
High Frequency Reference Register FMPLL_0
(CMU_0_HFREFR_A)
R/W 0x0000_0FFF on page 4-113