ST SPC560P34 - CTU Interrupt;Dma Requests; Table 311. CTU Interrupts

Cross Triggering Unit (CTU) RM0046
616/936 Doc ID 16912 Rev 5
The outgoing trigger event (all line are ORed) resets this flag to 0. TGS Overrun in the
sequential mode shall be generated under the following conditions:
– TGS is in sequential mode
– there is an incoming EV while the busy flag is high. the TGS_OSM bit is set.
The faults/errors flags in the CTU error flag register and in the CTU interrupt flag register
can be cleared by writing a 1 while writing a 0 has no effect. The CTU does not support a
write-protection mechanism.
24.7.3 CTU interrupt/DMA requests
The CTU can perform the following interrupt/DMA requests (15 interrupt lines):
● Error interrupt request (see Section 24.7.2, “CTU faults and errors) (1 interrupt line)
● ADC command interrupt request (1 interrupt line)
● Interrupt request on MRS occurrence (1 interrupt line)
● Interrupt request on each trigger event occurrence (1 interrupt line for each trigger
event)
● FIFOs interrupt requests and/or DMA transfer request (1 interrupt line for each FIFO)
● DMA transfer request on the MRS occurrence if GRE bit is set
The interrupt flags are shown in Table 3 1 1.
Table 311. CTU interrupts
Category Interrupt Interrupt function
Managed
individually
MRS_I MRS Interrupt flag (IRQ193)
T0_I Trigger 0 interrupt flag (IRQ194)
T1_I Trigger 1 interrupt flag (IRQ195)
T2_I Trigger 2 interrupt flag (IRQ196)
T3_I Trigger 3 interrupt flag (IRQ197)
T4_I Trigger 4 interrupt flag (IRQ198)
T5_I Trigger 5 interrupt flag (IRQ199)
T6_I Trigger 6 interrupt flag (IRQ200)
T7_I Trigger 7 interrupt flag (IRQ201)
ADC_I ADC command interrupt flag (IRQ206)
ORed onto
FIFO1_I (IRQ202)
FIFO_FULL0 This bit is set to 1 if the FIFO 0 is full.
FIFO_EMPTY0 This bit is set to 1 if the FIFO 0 is empty.
FIFO_OVERFLOW
0
This bit is set to 1 if the number of words exceeds the value set in the
threshold 0.
FIFO_OVERRUN0
This bit is set to 1 if a write operation occurs when corresponding
FIFO_FULL0 flag is set.