Nexus Development Interface (NDI) RM0046
910/936 Doc ID 16912 Rev 5
update a processor resource, this register is initialized with a data value to be written, and
an e_ori instruction is executed which uses this value as a substitute data value. The
Control State register FFRA bit forces the value of the WBBR
low
to be substituted for the
normal RS source value of the e_ori instruction, thus allowing updates to processor
registers to be performed (refer to Section for more detail on the CTL
FFRA
bit).
WBBR
low
and WBBR
high
are generally undefined on instructions which do not writeback a
result, and due to control issues are not defined on lmw or branch instructions as well.
Machine State Register (MSR)
The MSR is a 32-bit register used to read/write the Machine State Register. Whenever the
external command controller needs to save or modify the contents of the Machine State
Register, this register is used.This register is affected by the operations performed during
the debug mode and must be restored by the external command controller when returning
to normal mode.
36.13 Watchpoint Support
e200z0h supports the generation and signalling of watchpoints when operating in internal
debug mode (DBCR0
IDM
=1) or in external debug mode (DBCR0
EDM
=1). Watchpoints are
indicated with a dedicated set of interface signals. The jd_watchpoint[0:5] output signals
are used to indicate that a watchpoint has occurred.
Each debug address compare function (IAC1–4, DAC1–2) is capable of triggering a
watchpoint output. The DBCRx control fields are used to configure watchpoints, regardless
of whether events are enabled in DBCR0. Watchpoints may occur whenever an associated
event would have been posted in the Debug Status Register if enabled. No explicit enable
bits are provided for watchpoints; they are always enabled by definition (except during a
debug session). during a debug session. If not desired, the base address values for these
events may be programmed to an unused system address. MSR
DE
has no effect on
watchpoint generation.
External logic may monitor the assertion of these signals for debugging purposes.
Watchpoints are signaled in the clock cycle following the occurrence of the actual event. The
Nexus2+ module also monitors assertion of these signals for various development control
purposes.
Table 472. Watchpoint Output Signal Assignments
Signal Name Type Description
jd_watchpt[0] IAC1
Instruction Address Compare 1 watchpoint
Asserted whenever an IAC1 compare occurs regardless of being enabled
to set DBSR status
jd_watchpt[1] IAC2
Instruction Address Compare 2 watchpoint
Asserted whenever an IAC2 compare occurs regardless of being enabled
to set DBSR status
jd_watchpt[2] IAC3
Instruction Address Compare 3 watchpoint
Asserted whenever an IAC3 compare occurs regardless of being enabled
to set DBSR status
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