ST SPC560P34 - Table 49. Low-Power Peripheral Configuration Registers (ME_LP_PC0; Figure 61. Low-Power Peripheral Configuration Registers (ME_LP_PC0; Figure 62. Peripheral Control Registers (ME_PCTL0

RM0046 Mode Entry Module (MC_ME)
Doc ID 16912 Rev 5 167/936
Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)
These registers configure eight different types of peripheral behavior during non-run modes.
Peripheral Control Registers (ME_PCTL0…143)
These registers select the configurations during run and non-run modes for each peripheral.
Figure 61. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7)
Address 0xC3FD_C0A0 - 0xC3FD_C0BC Access: User read, Supervisor read/write, Test read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000
STOP0
0
HALT0
00000000
W
Reset0000000000000000
Table 49. Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) Field Descriptions
Field Description
STOP0
Peripheral control during STOP0
0 Peripheral is frozen with clock gated
1 Peripheral is active
HALT0
Peripheral control during HALT0
0 Peripheral is frozen with clock gated
1 Peripheral is active
Figure 62. Peripheral Control Registers (ME_PCTL0…143)
Address 0xC3FD_C0C0 - 0xC3FD_C14F Access: User read, Supervisor read/write, Test read/write
01234567
R 0
DBG_F LP_CFG RUN_CFG
W
Reset00000000