RM0046 FlexCAN
Doc ID 16912 Rev 5 553/936
influence on the bus when in ‘Bus Off’ state. The following are the basic rules for FlexCAN
bus state transitions.
● If the value of Tx_Err_Counter or Rx_Err_Counter increases to be greater than or equal
to 128, the FLT_CONF field in the Error and Status Register is updated to reflect ‘Error
Passive’ state.
● If the FlexCAN state is ‘Error Passive’, and either Tx_Err_Counter or Rx_Err_Counter
decrements to a value less than or equal to 127 while the other already satisfies this
condition, the FLT_CONF field in the Error and Status Register is updated to reflect
‘Error Active’ state.
● If the value of Tx_Err_Counter increases to be greater than 255, the FLT_CONF field in
the Error and Status Register is updated to reflect ‘Bus Off’ state, and an interrupt may
be issued. The value of Tx_Err_Counter is then reset to 0.
● If FlexCAN is in ‘Bus Off’ state, then Tx_Err_Counter is cascaded together with another
internal counter to count the 128th occurrences of 11 consecutive recessive bits on the
bus. Hence, Tx_Err_Counter is reset to 0 and counts in a manner where the internal
counter counts 11 such bits and then wraps around while incrementing the
Tx_Err_Counter. When Tx_Err_Counter reaches the value of 128, the FLT_CONF field
in the Error and Status Register is updated to be ‘Error Active’ and both error counters
are reset to zero. At any instance of dominant bit following a stream of less than 11
consecutive recessive bits, the internal counter resets itself to zero without affecting the
Tx_Err_Counter value.
● If during system start-up, only one node is operating, then its Tx_Err_Counter
increases in each message it is trying to transmit, as a result of acknowledge errors
(indicated by the ACK_ERR bit in the Error and Status Register). After the transition to
‘Error Passive’ state, the Tx_Err_Counter does not increment anymore by acknowledge
errors. Therefore the device never goes to the ‘Bus Off’ state.
● If the Rx_Err_Counter increases to a value greater than 127, it is not incremented
further, even if more errors are detected while being a receiver. At the next successful
message reception, the counter is set to a value between 119 and 127 to resume to
‘Error Active’ state.
Error and Status Register (ESR)
This register reflects various error conditions, some general status of the device and it is the
source of four interrupts to the CPU. The reported error conditions (bits 16–21) are those
that occurred since the last time the CPU read this register. The CPU read action clears bits
16–21. Bits 22–28 are status bits.
Figure 271. Error Counter Register (ECR)
Address:
Base + 0x001C Access: User read/write
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Rx_Err_Counter Tx_Err_Counter
W
Reset0000000000000000
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